Nanowire field-effect device with multiple gates

Abstract

The present invention relates to a semiconductor device (1) comprising: at least a nanowire (2) configured to comprise: at least a source region (3) comprising a corresponding source semiconductor material, at least a drain region (4) comprising a corresponding drain semiconductor material and at least a channel region (5) comprising a corresponding channel semiconductor material, the channel region (5) being arranged between the source region (3) and the drain region (4), at least a gate electrode (6) that is arranged relative to the nanowire (2) to circumferentially surround at least a part of the channel region (5), and at least a strain gate (7) that is arranged relative to the nanowire (2) to circumferentially surround at least a part of a segment of the nanowire (2), the strain gate (7) being configured to apply a strain to the nanowire segment (8), thereby to facilitate at least an alteration of the energy bands corresponding to the source region (3) relative to the energy bands corresponding to the channel region (5).

Description

Technical field [0001] The invention relates to a semiconductor device and a manufacturing method thereof. Background technique [0002] Tunnel field effect transistors (FETs) can be used in several applications including high-speed switching and logic circuits. Unlike the case of other types of FETs, the inverse subthreshold slope of the tunnel FET is not limited to 60 mV / dec at room temperature as determined by the Boltzmann tailing of Fermi statistics. Therefore, the tunnel FET can potentially have a faster turn-on than the previously proposed device, that is, the bias range used to facilitate the transition from the "on" conductive state to the "off" non-conductive state is smaller than the previously proposed device It is possible to reduce both the threshold value and the operating voltage without corresponding degradation of device performance. This makes tunnel FETs particularly suitable for applications where reduced power consumption is desired. [0003] Until recently...

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Problems solved by technology

For example, when the tunnel FET is based on a vertical nanowire process, another challenge will be experienced in creating a steep tunnel junction at the base of the nanowire

Additionally, in some materials, chemical doping of both polarities can be challenging, for example due to difficulties associated with incorporation of the desired doped atoms during growth.

[0010] See now Lee et al., Applied Physics Letters, Vol. 85, pp. 145-147, 2004, reporting that electrostatic doping can mitigate some of the disadvantages associated with impurity doping, especially with temperature-constrained materials (such as III-V systems) related doping, and in which sufficiently activated dopants of one or both polarities are achieved by impurity doping and / or other previously proposed methods with Si The situation is challenging

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