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Transistor including multi-layer reentrant profile

一种晶体管、材料层的技术，应用在晶体管、半导体器件、电气元件等方向，能够解决难以控制沉积层厚度等问题

Inactive Publication Date: 2013-09-04
EASTMAN KODAK CO
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, it is difficult to control the thickness of the deposited layer

Method used

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  • Transistor including multi-layer reentrant profile
  • Transistor including multi-layer reentrant profile
  • Transistor including multi-layer reentrant profile

Examples

Experimental program
Comparison scheme
Effect test

example 1

[0053] On a 62.5 mm square glass substrate, a 117 nm layer of chromium was deposited by sputter evaporation. On this layer, a 300 nm layer of aluminum was deposited by sputter coating. On the sample, another 117 nm layer of chromium was deposited by sputtering.

[0054] Microposit S1805 resist (Rohm and Haas Electronic Materials LLC, Marlborough, MA) placed on a heating plate was spun at 1000 rpm at 115 degrees Celsius. A patterned layer of photoresist was formed by coating for 60 seconds, and then processed on a Cobilt mask aligner (Cobilt Model CA-419, available from Computervision Corporation, Sunnyvale, CA) ), expose for 75 seconds through a glass / chrome contact mask containing lines, using only the edge of the glass substrate as a low-resolution or coarse alignment. Samples were then developed for 80 seconds in Microposit MF-319 developer (Rohm and Haas Electronic Materials, LLC, Marlborough, MA) and rinsed in DI water for 5 minutes.

[0055] The exposed chromium was e...

example 2

[0060] On a 62.5 mm square glass substrate, a 140 nm aluminum layer was deposited by thermal evaporation. On this layer, a 460 nm layer of molybdenum was deposited by sputter coating. On said samples, a 140 nm layer of aluminum was deposited by thermal evaporation.

[0061] Photoresist was patterned by spin coating Microposit S1805 resist (Rohm and Haas Electronic Materials, LLC, Marlborough, MA) placed on a hot plate at 115 degrees Celsius at 1000 rpm for 60 seconds layer, then on a Cobilt mask aligner (Cobilt Model CA-419, available from Computer Vision, Sunnyvale, CA), using only the edge of the glass substrate as a low-resolution or coarse alignment, by A glass / chrome contact mask containing lines was exposed for 75 seconds. Samples were then developed for 80 seconds in Microposit MF-319 developer (Rohm and Haas Electronic Materials, LLC, Marlborough, MA) and rinsed in DI water for 5 minutes. This not only develops the photoresist but also etches through the exposed alu...

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PUM

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Abstract

A transistor includes a substrate. A first electrically conductive material layer is positioned on the substrate. A second electrically conductive material layer is in contact with and positioned on the first electrically conductive material layer. A third electrically conductive material layer is in contact with and positioned on the second electrically conductive material layer. The third electrically conductive material layer overhangs the second electrically conductive material layer.

Description

technical field [0001] The present invention relates generally to semiconductor devices, and more particularly, to transistor devices. Background technique [0002] In semiconductor processing technology, a flat substrate surface that is horizontal to the wafer surface is patterned by photolithography combined with a selective etching process. During the processing of integrated circuits, reliefs with distinct topography are formed on the surface of a wafer or substrate. Typically, this type of relief comprises surfaces that are inclined or perpendicular to the substrate surface. As the size of integrated circuits continues to shrink, it is increasingly necessary to pattern vertical or inclined device surfaces in order to functionally differentiate the devices in their perpendicularity while still maintaining pattern alignment. Examples of these types of semiconductor devices include deep trench capacitors, stacked capacitors, and vertical transistors. [0003] Currently,...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L29/786H01L29/66
CPCH01L29/66787H01L29/78642
Inventor 李·威廉·塔特雪比·佛瑞斯特·尼尔森
Owner EASTMAN KODAK CO