Manufacturing method for gate dielectric layer and manufacturing method for transistor

Abstract

The invention provides a manufacturing method for a gate dielectric layer and a manufacturing method for a transistor. The manufacturing method for the gate dielectric layer comprises the steps that an interface layer is formed on a substrate by the adoption of a thermal growth method; a high-k gate dielectric layer is formed on the interface layer; surface processing is conducted on the interface layer or the high-k gate dielectric layer by the adoption of aqueous solution containing O3 or H2SO4 and H2O2. According to the manufacturing method for the gate dielectric layer and the manufacturing method for the transistor, due to the facts that the best interface layer is formed by the adoption of the thermal growth method, and the surface processing is conducted on the interface layer or the high-k gate dielectric layer by the adoption of the aqueous solution containing O3 or H2SO4 and H2O2, a large number of OH keys which are suitable for improving the coverage rate of the high-k gate dielectric layer are formed on the surface of the interface layer or the high-k gate dielectric layer, the high-k gate dielectric layer can nucleate more easily on the interface layer, and interfacial characterization between the interface layer and the high-k gate dielectric layer is improved.

Description

technical field [0001] The invention belongs to the field of manufacturing semiconductor integrated circuits, and in particular relates to a method for manufacturing a gate dielectric layer. In addition, the invention also relates to a method for manufacturing a transistor. Background technique [0002] Since the 1960s, the integrated circuit manufacturing process has been developing rapidly following Moore's Law. The feature size of CMOS devices has been continuously reduced according to a certain ratio, while its performance and power consumption have been continuously optimized. According to the prediction of ITRS in 2007, after 2009, the EOT (Equivalent Oxide Thickness) of the gate dielectric layer of high-performance CMOS devices will be reduced to below 1nm. At this size, conventional SiO 2 The gate dielectric material exposes serious problems such as excessive gate leakage current, reduced reliability, and easy diffusion of impurities. By introducing a high-k gate ...

AI Technical Summary

Problems solved by technology

The interface layer formed by the thermal growth method has better quality, but its disadvantages are: the high-k gate dielectric layer is difficult to nucleate on its surface and the coverage on its surface is low, resulting in the interface layer and the high-k gate dielectric There is a large amount of interface charge between the layers, which affects the interface characteristics between the interface layer and the high-k gate dielectric layer

The surface of the interface layer formed by the chemical growth method has a large number of OH bonds, which facilitates the growth of the high-k gate dielectric layer and improves the coverage of the high-k ga

Images