Manufacturing method for gate dielectric layer and manufacturing method for transistor

A manufacturing method and gate dielectric layer technology, which are applied in the manufacture of gate dielectric layers and the field of transistor manufacturing, can solve the problems of poor interface characteristics, affecting the interface characteristics of the interface layer and high-k gate dielectric layer, and poor quality of the interface layer. To achieve the effect of improving the interface characteristics
CN103295891AActive Publication Date: 2013-09-11SEMICON MFG INT (SHANGHAI) CORP
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Patent Information

Authority / Receiving Office
CN · China
Current Assignee / Owner
SEMICON MFG INT (SHANGHAI) CORP
Publication Date
2013-09-11

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Abstract

The invention provides a manufacturing method for a gate dielectric layer and a manufacturing method for a transistor. The manufacturing method for the gate dielectric layer comprises the steps that an interface layer is formed on a substrate by the adoption of a thermal growth method; a high-k gate dielectric layer is formed on the interface layer; surface processing is conducted on the interface layer or the high-k gate dielectric layer by the adoption of aqueous solution containing O3 or H2SO4 and H2O2. According to the manufacturing method for the gate dielectric layer and the manufacturing method for the transistor, due to the facts that the best interface layer is formed by the adoption of the thermal growth method, and the surface processing is conducted on the interface layer or the high-k gate dielectric layer by the adoption of the aqueous solution containing O3 or H2SO4 and H2O2, a large number of OH keys which are suitable for improving the coverage rate of the high-k gate dielectric layer are formed on the surface of the interface layer or the high-k gate dielectric layer, the high-k gate dielectric layer can nucleate more easily on the interface layer, and interfacial characterization between the interface layer and the high-k gate dielectric layer is improved.
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Description

technical field

[0001] The invention belongs to the field of manufacturing semiconductor integrated circuits, and in particular relates to a method for manufacturing a gate dielectric layer. In addition, the invention also relates to a method for manufacturing a transistor. Background technique

[0002] Since the 1960s, the integrated circuit manufacturing process has been developing rapidly following Moore's Law. The feature size of CMOS devices has been continuously reduced according to a certain ratio, while its performance and power consumption have been continuously optimized. According to the prediction of ITRS in 2007, after 2009, the EOT (Equivalent Oxide Thickness) of the gate dielectric layer of high-performance CMOS devices will be reduced to below 1nm. At this size, conventional SiO 2 The gate dielectric material exposes serious problems such as excessive gate leakage current, reduced reliability, and easy diffusion of impurities. By introducing a high-k gate ...

Claims

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