A kind of graphene transistor manufacturing method based on self-alignment technology
A manufacturing method, graphene technology, applied in transistors, semiconductor/solid-state device manufacturing, semiconductor devices, etc., can solve problems such as large channel resistance, and achieve the effects of improving performance, avoiding pollution, and reducing spacing
Active Publication Date: 2015-12-02
THE 13TH RES INST OF CHINA ELECTRONICS TECH GRP CORP
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Problems solved by technology
After several years of research, the graphene transistor current cutoff frequency f T It has reached 427GHz, but it is still far from the ideal value. The large channel resistance is one of the main factors affecting graphene devices
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[0045] A method for manufacturing graphene transistors based on self-alignment technology, comprising the following steps:
[0046] 1) Form a graphene layer 4 on a substrate 1, such as figure 1 shown;
[0047] 2) Deposit a metal layer 5 on the graphene layer 4, such as figure 2 shown;
[0048] 3) On the metal layer 5, the required area is covered by the photoresist pattern 6, such as image 3 shown;
[0049] 4) Use the photoresist pattern 6 as a mask to remove the exposed metal, such as Figure 4 shown;
[0050] 5) Use the photoresist pattern 6 as a mask to etch the exposed graphene, and then remove the photoresist, such as Figure 5 shown;
[0051] 6) Form the metal electrodes of the source 7, the gate 8 and the drain 9, wherein the source 7 and the drain 9 are connected to the metal of the active area, such as Figure 6 and 7 shown;
[0052] 7) Between the source electrode 7 and the drain electrode 9, a gate mask pattern 10 is formed with photoresist, such as Fi...
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Abstract
A method for manufacturing a graphene transistor based on self-aligning technology, the method comprising: on a substrate (1), forming successively graphene material (4), a metal film (5), and photoresist patterns (7) formed by lithography, removing the metal film and the graphene material uncovered by the photoresist, forming an active area, and metal electrodes (7, 8, 9) of a source, a gate, and a drain of the transistor, connecting the metal electrodes (7, 9) of the source and the drain with the metal in the active area, and forming gate photoresist patterns (10) between the source and the drain by lithography, etching off the exposed metal, forming successively a seed layer (11), a gate dielectric layer (12), and gate metal (13) on the exposed graphene surface, and finally forming a graphene transistor. The distance between the gate-source and the gate-drain is reduced, and performance of the graphene transistor is improved.
Description
technical field [0001] The invention relates to the technical field of manufacturing methods of semiconductor devices. Background technique [0002] Graphene is a new carbonaceous material with an ideal two-dimensional crystal structure. It is the material with the best electrical conductivity known so far. 7 cm / s, carrier mobility greater than 200000cm 2 / Vs, suitable for making UHF devices. After several years of research, the graphene transistor current cutoff frequency f T It has reached 427GHz, but it is still far from the ideal value. The large channel resistance is one of the main factors affecting graphene devices. As the size of the device decreases, the channel resistance is basically equivalent to the channel resistance of the device, which significantly affects the device performance. Therefore, the channel resistance is reduced, that is, the distance between the gate source and the gate drain is reduced as much as possible, thereby improving device performa...
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IPC IPC(8): H01L21/336H01L21/28
CPCH01L29/7781H01L29/1606H01L29/42364H01L29/42376H01L29/66045H01L29/66439H01L21/3081
Inventor 李佳冯志红蔚翠刘庆彬何泽召王晶晶
Owner THE 13TH RES INST OF CHINA ELECTRONICS TECH GRP CORP