ADC (analog-to-digital converter) data organization system with high storage efficiency and ADC data organization method

Abstract

The invention discloses an ADC (analog-to-digital converter) data organization system with high storage efficiency and an ADC data organization method. The ADC data organization system comprises a data collection and storage module, a data splicing and storage module, a remaining data storage module, a data selection module and a time sequence control module, wherein the data collection and storage module is used for collecting data and transmitting the collected data to the data splicing and storage module and the remaining data storage module; and the time sequence control module is used for controlling the data of the data splicing and storage module and the remaining data storage module to be spliced, controlling the data selection module to output the spliced data to a data end, and outputting a corresponding enable signal to an enable end at the same time. According to the ADC data organization system, non 2n-bit ADC data is organized through a splitting and splicing method, so that the seamless storage of the collected data in a dynamic random access memory is achieved, the storage space of the dynamic random access memory is saved, the storage of invalid data is avoided, the data transmission efficiency is improved, and the dynamic random access memory can work under lower work clock frequency.

Description

technical field [0001] The invention relates to the fields of data acquisition and FPGA digital logic design, in particular to an ADC data organization system with high storage efficiency and a method thereof. Background technique [0002] As a practical technology, data acquisition has been applied in many fields such as vibration testing and transient information analysis. The current data acquisition system generally uses FPGA as the core of data transmission and control, and DRAM as the buffer medium. For digits of 2 n The collected data can generate 8-bit or 16-bit data through simple serial-to-parallel conversion, and then store it in the dynamic random access memory through the asynchronous FIFO. And for digits other than 2 n ADC, the collected data usually generates 8-bit or 16-bit data through serial-to-parallel conversion combined with zero-filling method, and then stores it in DRAM through asynchronous FIFO. Although this method with zero-filling is simple to i...

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Problems solved by technology

[0008] Although the method described in this patent can realize the storage of arbitrary byte da

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