Preparation method for silica-based gallium arsenide material with high quality and low surface roughness

A silicon-based gallium arsenide, low surface technology, applied in the field of silicon-based gallium arsenide material preparation, can solve the problems of low surface roughness and achieve the effect of low polishing rate

Active Publication Date: 2013-09-18
INST OF SEMICONDUCTORS - CHINESE ACAD OF SCI
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Problems solved by technology

[0007] The purpose of the present invention is to provide a high-quality, low-surface-roughness silicon-based gallium arsenide material preparation method to solve the problem of t

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  • Preparation method for silica-based gallium arsenide material with high quality and low surface roughness
  • Preparation method for silica-based gallium arsenide material with high quality and low surface roughness

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[0021] See figure 1 and figure 2 As shown, the present invention provides a method for preparing a silicon-based gallium arsenide material with high quality and low surface roughness, including the following steps:

[0022] Step 1: A germanium layer 2 is grown on a silicon substrate 1. The silicon substrate 1 is a (100) substrate that is 4° in the [011] direction, and its size mainly depends on the three equipment required in this method: ultra-low vacuum chemical vapor deposition (UHVCVD), metal organic chemical vapor deposition ( MOCVD) and polishing equipment, the epitaxial wafer size of the three equipment needs to be the same, which can be 2 inches to 12 inches, or even larger; the growth of the germanium layer 2 adopts UHVCVD, and adopts two cycles of low temperature germanium seed layer and high temperature germanium layer. Technology, this step is a key step to obtain high-quality gallium arsenide, and the defect density of the germanium layer is required to be 1E5cm -2...

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Abstract

The invention discloses a preparation method for silica-based gallium arsenide material with high quality and low surface roughness. The preparation method comprises the following steps: step 1, a germanium layer is grown on a silicon substrate; step 2, the silicon substrate on which the germanium layer is grown is placed in an MOCVD (metal-organic chemical vapor deposition) reaction chamber to be subjected to annealing for the first time; step 3, a low-temperature gallium arsenide nucleating layer and a high-temperature gallium arsenide layer are grown on the germanium layer in sequence to form a sample; step 4, the sample is polished and rinsed; step 5, the sample is put in the MOCVD reaction chamber to be subjected to annealing for the second time; and step 6, a gallium arsenide cover layer is grown on the surface of the sample, and the preparation of the silica-based gallium arsenide material is finished. The preparation method for the silica-based gallium arsenide material with high quality and low surface roughness can solve the transition problem of the silicon substrate to III-V material and establishes the basis of substrate for silica-based gallium arsenide photoelectric and microelectronic devices.

Description

technical field [0001] The invention belongs to the field of semiconductor substrates, in particular to a method for preparing a silicon-based gallium arsenide material with high quality and low surface roughness, which combines ultra-high vacuum chemical vapor deposition with MOCVD to obtain a silicon-based gallium arsenide substrate Bottom, used in gallium arsenide-based microelectronics and optoelectronics. Background technique [0002] Silicon is and will be the basic material of the microelectronics industry, and most semiconductor devices still use silicon as the substrate material. As a carrier, silicon's low density, high thermal conductivity, low cost, and mature technology that can reach 12 inches and larger sizes make it an irreplaceable substitute for the microelectronics industry. At the same time, due to its high electron mobility, direct band gap and other characteristics, gallium arsenide material is the first compound semiconductor material widely used in o...

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Application Information

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IPC IPC(8): H01L21/205C30B25/18
Inventor 周旭亮于红艳米俊萍潘教青王圩
Owner INST OF SEMICONDUCTORS - CHINESE ACAD OF SCI
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