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chip packaging

A chip packaging and solder ball technology, applied in electrical components, electrical solid devices, circuits, etc., can solve the problems of high product cost and difficult processing, and achieve the effect of increasing the pass rate, increasing the distance, and increasing the width of the line.

Active Publication Date: 2016-05-18
北京君正集成电路股份有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] The purpose of the present invention is to propose a chip package, which aims to solve the problems of high product cost and difficult processing caused by the traditional chip package, which can only lay out lines with a width of 0.075mm.

Method used

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Embodiment Construction

[0010] The technical solutions of the present invention will be described in further detail below with reference to the accompanying drawings and embodiments.

[0011] figure 2 It is a schematic structural diagram of chip packaging according to an embodiment of the present invention, such as figure 2 As shown, the chip package of the embodiment of the present invention includes a substrate 201 and solder balls 202. The chip package of the embodiment of the present invention adopts a ball grid array package, and the solder balls 202 are distributed in an array on the substrate 201. Several rows and A series of solder balls 202 . The substrate 201 is a square with a side length D1 of 4.0 mm; eight solder balls 202 are distributed in each row, and eight solder balls 202 are distributed in each column, and the diameter D2 of the solder balls 202 is 0.25 mm; the outermost row of matrix solder balls The row spacing D3 from the second outer row is 0.45 mm, and the column spacing ...

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PUM

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Abstract

The invention relates to a chip package. The chip package comprises a substrate and solder balls, wherein the solder balls are distributed on the substrate in an array, the row spacing between the outmost row and the secondarily outmost row of the array type solder balls is smaller than the row spacing between other adjacent rows, and the column spacing between the outmost column and the secondarily outmost column of the array type solder balls is smaller than the column spacing between other adjacent columns. According to the chip package disclosed by the invention, by appropriately shortening the distance between the solder balls not requiring wiring and increasing the distance between the solder balls requiring wiring on the premise of not increasing the size of a chip, wire width is increased, product cost and processing difficulty are effectively reduced, and the qualified rate of products is significantly increased.

Description

technical field [0001] The invention relates to the field of chip packaging, in particular to a chip ball grid array packaging. Background technique [0002] Electronic products have entered the era of SMT (Surface Mount Technology, Surface Mount Technology). At present, with the development of electronic products in the direction of portable and miniaturization, the external dimensions of mounted components are gradually miniaturized, and the packaging pitch of mounted components is developing towards finer pitches, especially It is a BGA (BallGridArray, ball grid array package) with a pitch of 0.5mm and below 0.5mm, which requires high wiring accuracy on the PCB (Printed Circuit Board, printed circuit board), and the wiring is difficult. [0003] figure 1 It is a schematic diagram of a chip package structure in the prior art, such as figure 1 As shown, the chip side length d1 of the prior art is 4.0 mm, and the distance d2 between adjacent solder balls is 0.5 mm. Due to ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L23/488
Inventor 王坤
Owner 北京君正集成电路股份有限公司