Optimal Method of Task Scheduling for Spaceborne Data Transmission System
A technology for onboard data transmission and task scheduling, which is applied in the field of data processing of aerospace onboard electronic systems, can solve problems such as low system efficiency and limited data processing scale, improve task scheduling control capabilities, and reduce reconfiguration Time overhead, the effect of increasing the scale of FPGA data processing
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specific Embodiment approach 1
[0029] Specific implementation mode 1. Combination figure 1 Describe this embodiment in detail, the spaceborne digital transmission system described in this embodiment includes a high-resolution CCD camera 1, a large-capacity solid-state memory 2, a reconfigurable coprocessor 3, a modem 4 and a ground receiving station 5,
[0030] The image output end of the high-resolution CCD camera 1 is connected to the image input end of the large-capacity solid-state memory 2,
[0031] The image data output end of the large-capacity solid-state memory 2 is connected to the image data input end of the reconfigurable coprocessor 3,
[0032] The image data output end of the reconfigurable coprocessor 3 is connected to the image data input end of the modem 4,
[0033] The modem 4 transmits the image data to the ground receiving station 5 through the data transmission antenna.
[0034] The high-resolution CCD camera 1 described in this embodiment is the main payload of a remote sensing satel...
specific Embodiment approach 2
[0037] Embodiment 2. The difference between this embodiment and the on-board data transmission system described in Embodiment 1 is that the reconfigurable coprocessor 3 includes a processor chip 3-1, an FPGA chip 3-2 and a high-speed flash memory chip 3 -3,
[0038] The image data input end of the FPGA chip 3-2 is connected to the image data output end of the large-capacity solid-state memory 2,
[0039] The temporary data end of the FPGA chip 3-2 is connected to the temporary data end of the high-speed flash memory chip 3-3,
[0040] The image data control end of the FPGA chip 3-2 is connected to the image data control end of the processor chip 3-1,
[0041] The image data output end of the processor chip 3 - 1 is connected to the image data input end of the modem 4 .
[0042] The reconfigurable coprocessor 3 described in this embodiment has a strong parallel computing capability, combines the floating-point operation unit and the error detection and error correction module...
specific Embodiment approach 3
[0044] Embodiment 3. The difference between this embodiment and the on-board data transmission system described in Embodiment 2 is that the processor chip 3-1 adopts a chip model: TSC695.
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