Inter-processor communication method and system on chip

A system-level chip and communication method technology, which is applied in the communication method between processors and the SOC field, can solve problems such as not easy to expand, and achieve the effects of improving mailbox resource utilization, improving use flexibility, and saving implementation costs

Inactive Publication Date: 2013-09-25
이노피데이인코포레이티드 +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Moreover, it is not easy to expand. When the system adds processors, the structure and design of the mailbox need to be greatly modified.

Method used

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  • Inter-processor communication method and system on chip
  • Inter-processor communication method and system on chip

Examples

Experimental program
Comparison scheme
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Embodiment 1

[0029] refer to figure 1 , shows a flow chart of steps of an inter-processor communication method according to Embodiment 1 of the present invention.

[0030] The inter-processor communication method in this embodiment includes the following steps:

[0031] Step S102: the first processor in the SOC writes information to the corresponding storage space through at least one channel in the mailbox corresponding to the first processor.

[0032] Wherein, the mailbox is allocated by the SOC for the communication between the first processor and the second processor in the SOC, and each mailbox includes multiple channels.

[0033] In this embodiment, the SOC includes multiple processors, and the multiple processors include a first processor and a second processor. In a specific application, the number of processors is determined by system requirements, and at least two processors are included in an SOC using a mailbox. In the present invention, the specific number of processors inc...

Embodiment 2

[0045] refer to figure 2 , shows a flow chart of steps of a method for inter-processor communication according to Embodiment 2 of the present invention.

[0046] The inter-processor communication method in this embodiment includes the following steps:

[0047] Step S202: setting a mailbox in the SOC.

[0048] In this embodiment, the setting mailbox includes multiple channels, a status register indicating the status of the multiple channels, an initiation request register for applying for the multiple channels, and a processing completion register indicating the completion of reading information of the multiple channels. Wherein, the register corresponding to the processor (the first processor in this embodiment) that writes data includes an initiation request register and a status register; and the processor that reads data (the second processor in this embodiment) Corresponding registers include a processing completion register and a status register. That is, the status r...

Embodiment 3

[0065] refer to image 3 , shows a flow chart of steps of an inter-processor communication method according to Embodiment 3 of the present invention.

[0066] The inter-processor communication method in this embodiment includes the following steps:

[0067] Step S302: setting a mailbox in the SOC.

[0068] In this embodiment, each mailbox resource in the SOC is set to include a 32-bit status register (CHNL_STTS), a 1-bit request interrupt (REQ_INT) and a 1-bit processing completion interrupt (ACK_INT); in addition, in order to facilitate multiple processors to complete the For mailbox request and processing completion control, two additional 32-bit interface registers need to be implemented, one is the initiation request register (CHNL_SET), and the other is the processing completion register (CHNL_CLR). The structure of the above-mentioned mailbox is as follows Figure 4 shown. Among them, CHNL_STTS indicates the status of the 32 channels corresponding to the mailbox. Set ...

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PUM

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Abstract

The invention provides an inter-processor communication method and a system on chip (SOC). The inter-processor communication method comprises of the steps of using a first processor in the SOC to write information into a memory space through at least one channel in a mailbox; configuring channel occupancy information of the mailbox after information writing is finished and sending an interruption request to a second processor, confirming the channel in the mailbox with written information according to the configured channel occupancy information of the mailbox after the second processor receives the interruption request, and reading the information from the memory space corresponding to the confirmed channel; receiving the information read by the second processor, updating the configured channel occupancy information of the mailbox, then sending a processing completion interruption request, and releasing occupancy of the channel finishing information reading in the mailbox according to the updated channel occupancy information of the mailbox. By means of the inter-processor communication method and the SOC, the resource utilization rate of the mailbox is improved.

Description

technical field [0001] The present invention relates to the technical field of communication, in particular to a communication method between processors and an SOC (System On Chip, system-on-chip). Background technique [0002] SOC, also known as system-on-chip or system-on-chip, can be understood as an integrated circuit that includes a microprocessor / microcontroller, memory, and other dedicated functional logic. With the continuous improvement of chip integration, more and more processors are integrated in SOC chip design to work in parallel to meet people's increasing data processing capability requirements. [0003] For example, a wireless communication processor in a typical SOC, in addition to the application CPU, usually also needs to integrate baseband-related MCU (Micro Control Unit, micro control unit), DSP (Digital Signal Processor, digital signal processor), including the central CPU and graphics image processing GPU (Graphic Processing Unit, graphics processing...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F15/167
Inventor 周卓王艳龙
Owner 이노피데이인코포레이티드
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