Looking for breakthrough ideas for innovation challenges? Try Patsnap Eureka!

NMOS transistor and method for forming the MOS transistor

A MOS transistor, transistor technology, applied in semiconductor devices, semiconductor/solid-state device manufacturing, electrical components, etc., can solve problems such as limited stress

Active Publication Date: 2016-02-17
SEMICON MFG INT (SHANGHAI) CORP
View PDF5 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0010] In the existing transistor formation method, the stress applied by the stress layer 102 to the channel region is limited

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • NMOS transistor and method for forming the MOS transistor
  • NMOS transistor and method for forming the MOS transistor
  • NMOS transistor and method for forming the MOS transistor

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0058] Currently, after the stress layer is formed, the semiconductor substrate needs to be annealed so that the stress in the stress layer is transferred to the channel region of the transistor. Expansion in the vertical direction causes the stress layer to deform, resulting in a reduction in the stress applied by the stress layer to the channel region, especially during the formation of the NMOS transistor, the silicon nitride layer of tensile stress is applied to the channel of the NMOS transistor The stress reduction in the region is particularly severe.

[0059] In order to solve the above problems, the inventor proposes a method for forming an NMOS transistor and a MOS transistor, wherein the method for forming the NMOS transistor includes: providing a semiconductor substrate on which an NMOS transistor is formed; A tensile-stressed silicon nitride layer is formed on the substrate, and the tensile-stressed silicon nitride layer covers the gate sidewall and top surface of...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

Disclosed are methods for forming an NMOS transistor and an MOS transistor. The method for forming the NMOS transistor comprises: providing a semiconductor substrate, wherein the NMOS transistor is formed on the semiconductor substrate; forming a tension silicon nitride layer on the semiconductor substrate, wherein the tension silicon nitride layer covers the side wall and the top surface of the gate of the NMOS transistor; forming a protection layer on the tension silicon nitride layer, wherein the protection layer exposes the tension silicon nitride layer on the top surface of the gate of the NMOS transistor; performing plasma treatment on the tension silicon nitride layer on the top surface of the gate of the NMOS transistor for the purpose of enhancing the young modulus of the tension silicon nitride layer on the top surface of the gate of the NMOS transistor; and removing the protection layer. In the embodiment of the invention, the stress of the tension layer is improved.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to an NMOS transistor and a method for forming the MOS transistor. Background technique [0002] With the rapid development of semiconductor manufacturing technology, semiconductor devices are developing towards higher component density and higher integration in order to achieve higher computing speed, larger data storage capacity, and more functions. Therefore, , the gates of complementary metal oxide semiconductor (ComplementaryMetalOxideSemiconductor, CMOS) transistors are becoming thinner and shorter than before. In order to obtain better electrical performance, it is usually necessary to improve the performance of semiconductor devices by controlling the carrier mobility. A key element of the technology is controlling the stress in the transistor channel. For example, by properly controlling the stress and increasing the mobility of carriers (electrons in n-channel ...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/336H01L21/28H01L21/265
Inventor 鲍宇
Owner SEMICON MFG INT (SHANGHAI) CORP
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Patsnap Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Patsnap Eureka Blog
Learn More
PatSnap group products

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic, Popular Technical Reports.

© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap|About US| Contact US: help@patsnap.com