Parallel-to-serial structure-based single pulse time domain amplifier

Abstract

The invention relates to a parallel-to-serial structure-based single pulse time domain amplifier. The parallel-to-serial structure-based single pulse time domain amplifier comprises a digital gain control unit used for controlling the on-off states of gain selection switches, n gain selection switches which are connected in parallel, and a parallel pulse-to-single pulse converter, wherein the n is a positive integer greater than 1; the parallel pulse-to-single pulse converter comprises n signal input ports and a signal output port; and the signal input ports are respectively in one-to-one correspondence with the gain selection switches. The parallel pulse-to-single pulse converter converts a single pulse signal which is input in a parallel way into a single pulse which is output in a serial way. By the time domain amplifier disclosed by the invention, a time amplification gain value which is linear and accurate and can be set dynamically can be realized; and the conversion rate of the TDC (time-digital converter) can be improved by applying the time domain amplifier to the TDC.

Description

technical field [0001] The present invention relates to a time-domain amplifier (time amplifier) ​​for a time-to-digital converter (TDC), especially a single-pulse time-domain amplifier based on a parallel-to-serial structure. Background technique [0002] The trend toward digitization of analog and mixed-signal circuits such as all-digital phase-locked loops (ADPLLs) and time-domain analog-to-digital converters (ADCs) has made time-domain-to-digital-domain converters (TDCs) increasingly important. In ADPLL, TDC and digital loop filter (DLF) have replaced traditional analog circuits (charge pump and loop filter); in time domain analog to digital converter ADC, voltage to time domain converter (V2T) and TDC replace the voltage domain comparator. [0003] Since most of these circuits are implemented digitally, their performance can be improved as CMOS process technology advances. However, due to the lack of high-precision, high-speed TDC, the performance of these circuits ha...

AI Technical Summary

Problems solved by technology

like figure 2 As shown, the SR latch works in the metastable region, but its disadvantages are: ① the gain of this time-domain amplifier is unpredictable and inaccurate; ② due to its metastable characteristics, it needs to be corrected; ③ the input linear range is very Small, the gain is not variable

However, this time-domain amplifier structure requires a sufficiently long delay time in order to avoid the overlap between pulses in the pulse train, so this will lead to a decrease in the TDC slew rate

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