Semiconductor device and manufacturing method thereof
A manufacturing method and semiconductor technology, applied in the fields of semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., can solve the problems of failure of semiconductor devices, connection between gate and source and drain regions, etc., and achieve the effect of improving yield
Active Publication Date: 2016-04-20
SEMICON MFG INT (SHANGHAI) CORP
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Problems solved by technology
[0005] However, when the metal material layer is deposited on the gate, the diffusion effect of the metal material layer along the horizontal direction in the gate sidewall becomes more and more obvious as the width of the gate sidewall continues to decrease, which easily causes the gate The connection with the source and drain regions forms a metal silicide bridge (SilicideBridge) problem, which in turn causes the failure of semiconductor devices
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[0036] In order to make the content of the present invention clearer and easier to understand, the content of the present invention will be further described below in conjunction with the accompanying drawings. Of course, the present invention is not limited to this specific embodiment, and general replacements known to those skilled in the art are also covered within the protection scope of the present invention.
[0037] Secondly, the present invention is described in detail by means of schematic diagrams. When describing the examples of the present invention in detail, for the convenience of explanation, the schematic diagrams are not partially enlarged according to the general scale, which should not be used as a limitation of the present invention.
[0038] figure 1 It is a schematic structural diagram of a semiconductor device in an embodiment of the present invention. Such as figure 1 As shown, the present invention provides a semiconductor device, including: a semico...
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The invention provides a semiconductor device and a method for manufacturing the semiconductor device. The semiconductor device comprises a semiconductor substrate, a grid structure located on the semiconductor substrate, a first side wall and a second side wall, wherein the first side wall is located on the side wall of the grid structure, the height of the first side wall is lower than hat that of the grid structure, the second side wall is located on the side wall of the grid structure and is located on the first side wall, and the width of the bottom surface of the second side wall is larger than that of the top surface of the first side wall. Because the first side wall and the second side wall are sequentially formed on the side wall of the grid structure, the width of the bottom surface of the second side wall is larger than that of the top surface of the first side wall to form an eave-type structure, metal materials are deposited on the first side wall and the second wall at intervals in the follow-up metal silicification process, and accordingly the problem that a source region and a drain region in the grid structure and the semiconductor substrate are communicated because of diffusion of the metal materials is effectively avoided and the yield of semiconductor devices is improved.
Description
technical field [0001] The invention relates to the field of integrated circuit manufacturing, in particular to a semiconductor device and a manufacturing method thereof. Background technique [0002] As the integration of semiconductor devices becomes higher and higher, the voltage and current required for the operation of semiconductor devices continue to decrease, and the switching speed of transistors is also accelerated, and the requirements for various aspects of semiconductor technology have been greatly increased. [0003] Metal-oxide-semiconductor (CMOS) devices include a core device layer and an interconnection layer. Structures such as gates, sources, and drains are formed in the core device layer. Structures such as electrode, source and drain are electrically drawn out. As the size of the device continues to decrease, the contact area between the metal interconnection and the gate, source and drain continues to shrink, and the influence of the parasitic resista...
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IPC IPC(8): H01L29/78H01L29/423H01L21/336
Inventor 鲍宇
Owner SEMICON MFG INT (SHANGHAI) CORP