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A kind of packaging method of igbt device and whole wafer igbt chip

A chip and device technology, applied in the field of semiconductor device manufacturing technology, can solve the problems of IGBT chips with different pressure, weak current carrying capacity, and low packaging area utilization, so as to avoid adverse effects and ensure reliability.

Active Publication Date: 2016-06-22
ZHUZHOU CRRC TIMES SEMICON CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, the IGBT prepared by the above method is formed by interconnecting and packaging multiple IGBT chips, and the utilization rate of the packaging area is low, resulting in a low utilization rate of the current-carrying area inside the device and weak current-carrying capacity; and each IGBT chip may come from a different This will lead to different thicknesses and electrical parameters of each IGBT chip, which will lead to different pressures on each IGBT chip during packaging and difficult control of the electrical parameters of the packaged IGBT device.

Method used

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  • A kind of packaging method of igbt device and whole wafer igbt chip
  • A kind of packaging method of igbt device and whole wafer igbt chip
  • A kind of packaging method of igbt device and whole wafer igbt chip

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Embodiment 1

[0069] Based on the above idea, an embodiment of the present application provides an IGBT device, and the IGBT device is packaged in a whole-wafer IGBT chip. The upper surface of the whole wafer IGBT chip includes: a central gate connection area and a plurality of emitter connection areas surrounding the central gate connection area, and its lower surface includes: a collector area, wherein the The emitter connection area on the surface of the failed cell area is thinned.

[0070] refer to figure 1 , the shown full-wafer IGBT chip includes: a full-wafer substrate 11, a gate interconnection layer arranged on the upper surface of the full-wafer substrate 11, a central gate arranged on the upper surface of the gate interconnection layer The electrode connection region 13 and the emitter interconnection layer surrounding the central gate connection region 13 .

[0071] The wafer substrate 11 includes: an active area and a terminal area 12 surrounding the active area; a plurality...

Embodiment 2

[0104] This embodiment provides a packaging method for a full-wafer IGBT chip, the upper surface of the full-wafer IGBT chip includes: a central gate connection region and a plurality of emitter connection regions surrounding the central gate connection region, The lower surface includes: a collector area.

[0105] refer to Figure 7 , the encapsulation method includes:

[0106] Step S11: Thinning the emitter connection region of the failed cell region of the whole-wafer IGBT chip.

[0107] In the traditional packaging process, in order to avoid the impact of the failure cell area on the performance of the IGBT device, the emitter pad is generally processed, such as hollowing out at a specific position of the emitter pad, and then when packaging, the hollowed out part and the The failure cell area is set correspondingly, so that the failure cell area is disconnected from the emitter electrode, so as to ensure the performance of the IGBT device. When aligning the hollowed ou...

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Abstract

The invention discloses an IGBT device and a packaging method for a full-wafer IGBT chip. The IGBT device includes: a full-wafer IGBT chip, the upper surface of which includes: a central grid connection area and a grid surrounding the central grid connection area. A plurality of emitter connection areas, the lower surface of which includes: a collector area, wherein the emitter connection area located on the surface of the failed cell area of ​​the chip has been thinned; a collector pad fixed on the lower surface of the chip and An emitter pad fixed on the upper surface of the chip; a collector electrode in electrical contact with the collector pad and an emitter electrode in electrical contact with the emitter pad; connected to the central gate connection area A gate lead-out line, the gate lead-out line is insulated from the emitter pad and the emitter electrode. The IGBT device avoids the adverse effect of the failure cell area in the whole wafer chip on the performance of the IGBT device.

Description

technical field [0001] The invention relates to the technical field of semiconductor device manufacturing technology, and more specifically, relates to an IGBT device and a packaging method for a full-wafer IGBT chip. Background technique [0002] The insulated gate bipolar transistor (InsulatedGateBipolarTransistor, referred to as IGBT) has the advantages of high input impedance of MOSFET devices and high-speed switching characteristics of power transistors (that is, giant transistors, GiantTransistor, referred to as GTR), and is widely used in AC motors, frequency converters, Switching power supply, lighting circuit, traction drive and other fields. [0003] When preparing IGBT devices, generally multiple independent IGBT cell regions are formed on the wafer (each IGBT cell region includes multiple IGBT cells), and multiple single-grain IGBT chips are obtained after cutting, each The chip includes independent cell emitters, cell collectors, and cell gates. Then, the qual...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L29/739H01L29/08H01L21/331H01L21/50
CPCH01L29/41741H01L29/66333H01L29/7395H01L29/0657H01L24/05H01L24/06H01L2224/05552H01L2224/0612H01L2924/10156H01L2924/13055H01L23/051H01L2924/13091H01L24/72H01L2924/00H01L29/0696
Inventor 李继鲁吴煜东彭勇殿
Owner ZHUZHOU CRRC TIMES SEMICON CO LTD