Multichannel RAM (random-access memory) reading/writing circuit and method

Abstract

The invention provides a multichannel RAM (random-access memory) reading / writing circuit and method. A plurality of RAMs are added in the circuit, a bus bridge, an arbiter and multiplexer cooperates, simpler circuit control logic is used to allow access bandwidth of RAM is increased greatly while system clock frequency is unchanged, and average system power consumption is unchanged. The multichannel RAM reading / writing circuit is simple, low in cost and easy to implement in a system.

Description

technical field [0001] The invention relates to the technical field of storage, in particular to a multi-channel read / write RAM circuit and method. Background technique [0002] At present, chips based on SoC (System on Chip, system-on-chip) architecture have been widely used in various electronic systems. On-chip RAM (Radom Access Memory, Random Access Memory) is an important part of the SoC system. It is generally used as instruction memory, data exchange space and temporary data storage space. The speed of each master device (Master) on the bus to access RAM becomes A key factor restricting system performance. The read / write operation of RAM under most current technologies must be delayed by one beat, that is, when doing read / write operations, the read / write data must always be valid in the next beat when the read signal is valid. Please refer to figure 1 , taking reading RAM as an example, CE in the figure is the enable signal of RAM, which is active at low level, and...

AI Technical Summary

Problems solved by technology

From the perspective of improving RAM access bandwidth, it is very convenient to use the AHB bus, but its bus arbitration and decoding mechanisms are relatively complicated. In some small systems, the use of the AHB bus will increase the design complexity of the entire system.

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