Looking for breakthrough ideas for innovation challenges? Try Patsnap Eureka!

Semiconductor device, process for producing semiconductor device, semiconductor substrate, and process for producing semiconductor substrate

A manufacturing method and semiconductor technology, which are applied in the manufacture of semiconductor/solid-state devices, semiconductor devices, transistors, etc., and can solve the problem of unclear factors affecting the interface energy level.

Inactive Publication Date: 2013-12-25
SUMITOMO CHEM CO LTD +3
View PDF4 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, the factors that affect the above-mentioned interface energy levels are not yet clear.

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Semiconductor device, process for producing semiconductor device, semiconductor substrate, and process for producing semiconductor substrate
  • Semiconductor device, process for producing semiconductor device, semiconductor substrate, and process for producing semiconductor substrate
  • Semiconductor device, process for producing semiconductor device, semiconductor substrate, and process for producing semiconductor substrate

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0124] For the purpose of investigating the interface level formed at the interface between a compound semiconductor and an insulating material forming its surface, an MIS diode was fabricated as an example of a semiconductor device. As an example of a Group 3-5 compound semiconductor having a zinc blende crystal structure, Si-doped N-type GaAs is used. MIS diodes are formed in the following order.

[0125] First, Si-doped N-type GaAs is formed as an example of a group 3-5 compound semiconductor having a zinc blende crystal structure. The Si-doped N-type GaAs is formed on the surface of the Si-doped N-type single crystal GaAs substrate. The aforementioned Si-doped N-type GaAs is obtained by epitaxial growth on the (111) A plane of the Si-doped N-type single crystal GaAs substrate. Accordingly, a Group 3-5 compound semiconductor having a (111)A plane on a plane parallel to the principal plane of the substrate is formed. Moreover, the electron concentration of the above-menti...

Embodiment 2

[0132] Manufacture of Al with Si-doped N-type single-crystal GaAs substrate, Si-doped N-type GaAs formed on the surface of the GaAs substrate, and (111) B plane in contact with Si-doped N-type GaAs 2 o 3 thin film, contact with Al 2 o 3 Thin film Au thin film, and Cr / Au ohmic electrode MIS diode formed on the back surface of the above-mentioned GaAs substrate. The MIS diode of Example 2 was manufactured in the same manner as in Example 1, except that Si-doped N-type GaAs was epitaxially grown on the (111)B plane of the Si-doped N-type single crystal GaAs substrate.

[0133] The electron concentration of the above Si-doped N-type GaAs is 2×10 16 / cm 3 . Meanwhile, the thickness is 1 μm. Using the obtained MIS diode, the interface energy level was measured in the same manner as in Example 1. The measurement of the interface energy level is carried out by measuring the capacitance-voltage characteristic of the MIS diode.

[0134] Figure 15 , represents the CV characteri...

Embodiment 3

[0142] use Figure 3 to Figure 10 The illustrated method fabricated a field effect transistor. On a p-type InP substrate, a compound semiconductor 120 of p-type InGaAs is epitaxially grown. The ratio of In and Ga is 0.53:0.47, and at the same time, the p-type carrier density is 3×10 16 cm -3 The p-type InGaAs is formed in the state, and the epitaxial growth is carried out under the condition that the (111) A plane is used as the surface. As the sacrificial film 360, Al with a thickness of 6 nm was formed by the ALD method. 2 o 3 After that, a photomask 390 was formed, and Si was ion-implanted. The condition of ion implantation is set to implant amount of 2×10 14 cm -2 , the accelerating voltage is 30keV.

[0143] After removing the photomask 390, RTA (rapid thermal annealing) is performed at 100° C. for 10 seconds to activate the implanted Si to form the source region 222 and the drain region 224 . By buffered hydrofluoric acid (BHF), dilute hydrofluoric acid (DHF), a...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

There is provided a semiconductor device that includes a III-V Group compound semiconductor having a zinc-blende-type crystal structure, an insulating material being in contact with the (111) plane of the III-V Group compound semiconductor, a plane of the III-V Group compound semiconductor equivalent to the (111) plane, or a plane that has an off angle with respect to the (111) plane or the plane equivalent to the (111) plane, and an MIS-type electrode being in contact with the insulating material and including a metal conductive material.

Description

[0001] This application is a divisional application with the application number of , the parent application number is 200980148632.X, the application date is November 27, 2009, and the title of the invention is a semiconductor device, a manufacturing method of a semiconductor device, a semiconductor substrate, and the manufacture of a semiconductor substrate method. technical field [0002] The present invention relates to a semiconductor device, a method for manufacturing the semiconductor device, a semiconductor substrate, and a method for manufacturing the semiconductor substrate. In addition, this application is the 2008 (Heisei 20) Ministry of Economy, Trade and Industry "About strategic technology development entrustment fee (nanoelectronics semiconductor new material and new structure technology development-including new material and new structure nanoelectronic device<(4) Research and development of III-V MISFET / III-V-On-Insulator (III-V-OI) MISFET formation process...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/336H01L21/28H01L29/423H01L29/49H01L29/78H01L29/786H01L29/94
CPCH01L29/045H01L29/20H01L29/7833H01L29/78681
Inventor 秦雅彦福原升山田永高木信一杉山正和竹中充安田哲二宫田典幸板谷太郎石井裕之大竹晃浩奈良纯
Owner SUMITOMO CHEM CO LTD
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Patsnap Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Patsnap Eureka Blog
Learn More
PatSnap group products

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic, Popular Technical Reports.

© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap|About US| Contact US: help@patsnap.com