Semiconductor device manufacturing method

Abstract

The invention discloses a semiconductor device manufacturing method, comprising: forming a gate stack structure on a substrate; sequentially depositing a first dielectric material layer and a second dielectric material layer on the substrate and the gate stack structure; using helium-containing The etching gas sequentially etches the second dielectric material layer and the first dielectric material layer to form the second sidewall and the first sidewall respectively. According to the semiconductor device manufacturing method of the present invention, the double-layer composite sidewall and the etching gas containing helium are used for two-step etching, which reduces the damage to the substrate and also reduces the complexity of the process. In addition, the valve can be optimized. Value voltage, effectively reduce EoT, improve gate control capability and drive current.

Description

technical field [0001] The invention relates to the field of semiconductor integrated circuit manufacturing, and more specifically, to a sidewall etching method. Background technique [0002] In VLSI manufacturing, dielectric spacers need to be made before the lightly doped drain (LDD) implantation process to prevent source-drain implantation of a larger dose from being too close to the channel to cause source-drain breakthrough, resulting in device failure and reduced yield. [0003] The current mainstream 65nm or even 45nm sidewall manufacturing process is: before the lightly doped drain (LDD) implantation process, first deposit or thermally grow a layer of silicon dioxide film, such as rapid thermal oxidation (RTO) growth Silicon dioxide on the left and right is used as a subsequent etching barrier to protect the substrate, especially the interface between the source and drain regions close to the channel region, from damage, so as to avoid the increase of defect densit...

AI Technical Summary

Problems solved by technology

In particular, the current sidewall etching technology is generally based on Ar-based gas, which is easy to cause damage to the substrate under the conditions of nanoscale devices, especially when the silicon oxide liner on the gate is extremely thin, oxygen plasma Easily penetrates thin oxide layers and reacts with the substrate, resulting in large silicon loss values

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