Low-temperature polycrystalline silicon thin film transistor array substrate, manufacturing method thereof and display device

Abstract

The invention provides a low-temperature polycrystalline silicon thin film transistor array substrate, a manufacturing method of the low-temperature polycrystalline silicon thin film transistor array substrate and a display device, and belongs to the field of the thin film transistor manufacturing technology. The low-temperature polycrystalline silicon thin film transistor array substrate comprises contact holes, wherein a source electrode and a drain electrode of the low-temperature polycrystalline silicon thin film transistor array substrate are connected with an active layer through the contact holes, and conductive patterns which are connected with the active layer are arranged at the bottoms of the contact holes. According to the technical scheme, good Ohmic contact can be formed between the source electrode of the low-temperature polycrystalline silicon thin film transistor array substrate and the active layer, and between the drain electrode of the low-temperature polycrystalline silicon thin film transistor array substrate and the active layer after etching of the contact holes is accomplished, and display quality of the display device is ensured.

Description

technical field [0001] The invention relates to the field of thin film transistor manufacturing technology, in particular to a low-temperature polysilicon thin film transistor array substrate, a manufacturing method thereof, and a display device. Background technique [0002] LTPS (low temperature polysilicon) has high carrier mobility due to its regular arrangement of atoms (10-300cm 2 / Vs), but also has a higher driving current, which can speed up the response time of liquid crystal, reduce the volume of TFT (thin film transistor), increase the transmission area, and obtain higher brightness and resolution. Therefore, the manufacturing process of thin film transistors is widely used. The active layer is prepared by LTPS. [0003] figure 1 with figure 2 Shown is a schematic structural diagram of an existing low-temperature polysilicon thin film transistor array substrate, wherein 10 is a substrate substrate, 11 is a buffer layer, 13 is an active layer, 14 is a gate insu...

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Problems solved by technology

in production figure 1 In the case of the array substrate shown, since the thickness of the gate insulating layer 14 and the interlayer insulating layer 16 is larger than the thickness of the active layer 13 (generally, the thickness of the gate insulating layer+interlayer insulating layer is greater than the thickness of the active layer by 10 In addition to the inhomogeneity of the deposited film and the etching process, when etching the contact holes of the gate insulating layer and the interlayer insulating layer, in order to ensure that the contact holes can reach the active layer on the entire substrate , it is necessary to achieve a higher amount of over-etch, and under the premise of ensuring the over-etch amount of the gate insulating layer and the interlayer insulating layer, the relatively thin active layer is extremely easy to form over-etch, affecting the source electrode and drain electrode. The ohmic contact with the active layer reduces the on-state current and affects the TFT characteristics, thereby affecting the display of the display device

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