Device and method for CPU (central processing unit) to access local bus on basis of PCIE (peripheral component interface express) protocol

Abstract

The invention discloses a device and a method for a CPU (central processing unit) to access a local bus on the basis of a PCIE (peripheral component interface express) protocol, which relate to the field of IPRAN (internet protocol radio access network). The device comprises a PCIE interface module, a data conversion module and a local bus interface module, wherein the PCIE interface module is used for realizing the PCIE underlying protocol, so that the device is used as one PCIE slave-end device to work under a PCIE system; the local bus interface module is used for simulating the time sequence of a traditional local bus and realizing the reading-writing access to an FPGA (field programmable gate array) local register or an external chip which is bridged through the FPGA. By Adopting the device and method, the highest possibility and performance can be obtained on the premise of consuming the least logic resource, the complexity in designing a PCIE interface transmission layer can be effectively simplified, the reading-writing efficiency of the system can be remarkably improved, and different local bus time sequences can be provided in real time.

Description

technical field [0001] The invention relates to the field of IPRAN, in particular to a device and method for a CPU accessing a local bus based on the PCIE protocol. Background technique [0002] With the continuous development of IP (Internet Protocol, Internet Protocol)-based transmission network, the main card CPU (Central Processing Unit, central processing unit) in IPRAN (IP Radio Access Network Carrier, IP-based wireless backhaul bearer network) equipment needs to communicate with Numerous core chips and sub-cards exchange data. In terms of device tree maintenance, interface simplification, and data transmission efficiency, the traditional localbus (local bus) is no longer up to the task. As a mature and widely used local bus technology, PCIE (Pedpherd Component Interconnect Express) is especially suitable for CPU and peripheral data due to its advantages of easy maintenance of device tree, simple interface and high data transmission rate. exchange. [0003] In variou...

AI Technical Summary

Problems solved by technology

[0005] (1) Low read and write efficiency: each read and write operation of the CPU can only transfer one register data

[0006] (2) The maintenance of the device tree is difficult and the scalability is poor: for different peripherals, the CPU distinguishes them through different chip selection signals, that is, as many peripherals as the CPU needs to access, it should provide as many chip selection signals

[0007] (3) The transmission rate is low, and the cost of hardware implementation is high: the local bus is a parallel bus, and the crosstalk problem of the parallel bus makes its reliable operating frequency only tens of megahertz, and the PCB wiring of the parallel bus is also very complicated

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