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Method for realizing self-aligned double pattern

A double pattern, self-alignment technology, applied in the direction of electrical components, semiconductor/solid-state device manufacturing, circuits, etc., can solve the problem of reducing the electrical performance of the device and achieve the effect of precise line width

Active Publication Date: 2016-01-06
SEMICON MFG INT (SHANGHAI) CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Any registration deviation will cause changes in the line width, and a slight deviation in the line width will change the parameters such as the width, length and resistance of the gate electrode in the produced semiconductor device, thereby reducing the electrical properties of the device. performance

Method used

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  • Method for realizing self-aligned double pattern
  • Method for realizing self-aligned double pattern
  • Method for realizing self-aligned double pattern

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Embodiment Construction

[0031] The present invention uses pulse etching and pulse deposition to form stepped sidewalls on both sides of the line or on the two walls of the opening, and then uses the sidewalls as a mask to etch the first dielectric layer that needs to be patterned, thereby Break through the bottleneck of existing lithography technology to form fine lines.

[0032] Wherein, pulse etching and pulse deposition in the present invention refer to periodical alternate etching and deposition, and said deposition refers to the technique of forming a new thin film layer on a dielectric layer, which includes the commonly described chemical vapor deposition , physical vapor deposition, atomic layer deposition, etc., also includes the self-generated process of forming a new thin film layer by reacting the exposed dielectric layer with the gas in the environment, such as the oxidation process in which polysilicon is oxidized to form silicon oxide on the surface.

[0033] In order to make the above ...

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Abstract

A method for achieving self-alignment type double patterns comprises the steps that a semiconductor substrate is provided; a first dielectric layer, a second dielectric layer, a hard mask layer and photoresist lines with first separation distances are sequentially formed on the semiconductor substrate from bottom to top; the hard mask layer is etched by using the photoresist lines as masks, and a plurality of hard mask layer lines are formed on the hard mask layer; by using the hard mask layer lines as the masks, the second dielectric layer is alternately etched n times and deposited n times in a periodic mode, an opening and side walls located on two sides of the opening are formed in the second dielectric layer, and each side wall comprises n layers of secondary side walls which are distributed in a step shape; the hard mask layer lines are removed; by using the side walls as the masks to etch the second dielectric layer and using the second dielectric layer as the masks to etch the first dielectric layer, lines with second separation distances are formed in the first dielectric layer. According to the method, etching and depositing are alternatively conducted in the periodic mode, the width of each side wall is accurately controlled, and therefore the line width of the patterns with small sizes can be formed through accurate control.

Description

technical field [0001] The invention relates to a semiconductor manufacturing process, in particular to a method for realizing a self-aligned double pattern. Background technique [0002] In order to integrate more and smaller transistors on a chip, new photolithography techniques must be developed to continuously reduce the size of transistors. Among them, a main development direction is to improve the minimum pitch or the minimum line width between two adjacent semiconductor patterns through double patterning technology. As far as the current development is concerned, the methods for achieving double patterning can be roughly divided into three categories: self-aligned double patterning (SADP), double patterning etching (DEDP) and double patterning exposure (LLE). [0003] Self-aligned double patterning (SADP) can form high-density parallel lines with small line width and pitch. The specific method is to first form lines by photolithography and etching, and then form a s...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/033H01L21/311
CPCH01L21/0332H01L21/0337H01L21/31144
Inventor 王新鹏张海洋
Owner SEMICON MFG INT (SHANGHAI) CORP