cmos and its formation method

Abstract

The invention provides a CMOS and a formation method thereof. The CMOS comprises a semiconductor substrate, a NMOS transistor and a PMOS transistor. The semiconductor substrate is provided with a first area and a second area. The NMOS transistor is located in the first area of the semiconductor substrate. The NMOS transistor comprises a first grid structure, first lifting source / drain regions and a first metal silicide contact region, wherein the first lifting source / drain regions are arranged on two sides of the first grid structure, and the first metal silicide contact region is arranged in the first lifting source / drain regions. The PMOS transistor is located in the second area of the semiconductor substrate. The PMOS transistor comprises a second grid structure, second lifting source / drain regions and a second metal silicide contact region, wherein the second lifting source / drain regions are arranged on two sides of the second grid structure, the top surfaces of the second lifting source / drain regions are higher than that of the first lifting source / drain regions, the second metal silicide contact region is arranged in the second lifting source / drain regions, and the thickness of the second metal silicide contact region is smaller than that of the first metal silicide contact region. According to the CMOS, influences of tensile stress generated by the second metal silicide contact region on PMOS transistor channel areas are reduced.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a CMOS and a forming method thereof. Background technique [0002] Metal-oxide-semiconductor (MOS) transistors are the most basic devices in semiconductor manufacturing. They are widely used in various integrated circuits. According to the main carrier and the type of doping during manufacturing, they are divided into NMOS and PMOS transistors. [0003] The prior art provides a method for forming a transistor. Please refer to Figure 1 to Figure 3 , is a schematic cross-sectional structure diagram of a method for forming a transistor in the prior art. [0004] Please refer to figure 1 , providing a semiconductor substrate 100, performing ion implantation on the semiconductor substrate 100 to form a well region 101; forming a gate structure on the surface of the semiconductor substrate 100, the gate structure comprising a gate located on the surface of the semiconduct...

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Problems solved by technology

[0007] The short channel effect of the above-mentioned transistor is easy to occur, and the mobility of carriers in the channel region is limited. In order to solve the above problems, the US patent application number US4998150 proposes a raised source and drain region ) transistors, including: a gate structure on the surface of the semiconductor substrate; raised source / drain regions on both sides of the gate structure, the surface of the raised source / drain region is higher than the surface of the semiconductor substrate; Metal silicide contact area on the surface of the source and drain regions

[0008] However, the aforementioned transistors with raised source / drain regions have limited performance

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