Multi-layer multi-chip fan-out structure and manufacturing method

Abstract

The invention provides a multi-layer multi-chip fan-out structure. The multi-layer multi-chip fan-out structure comprises a bearing plate, and a plurality of packaging sub bodies which are stacked are arranged on the bearing plate; at least one die is packaged into each packaging sub body; in each packaging sub body, the die is coated by a dielectric material of a dielectric layer, and the die is attached to a metal cushion block with the front face faces upwards; an RDL layer is arranged on the dielectric layer of each packaging sub body; a bonding pad of the front face of each die is electrically connected with the RDL layer of the corresponding packaging sub body where the die exists; insulating layers are arranged between adjacent packaging sub bodies, and the RDL layers of the adjacent packaging sub bodies are electrically connected through second interconnection holes between the layers. The metal cushion blocks in the bottom packaging sub bodies are pressed on the surface of the bearing plate, and the metal cushion blocks in the middle or top packaging sub bodies are pressed on the insulating layers of the packaging sub bodies; the surface of each top packaging sub body is provided with a solder mask layer in a distributed mode. According to the multi-layer multi-chip fan-out structure, three-dimensional multi-chip stacking can be easily achieved.

Description

technical field [0001] The invention relates to the field of microelectronic packaging, in particular to a stacked chip fan-out structure and a manufacturing method. Background technique [0002] Today's electronic packaging must not only provide protection for the chip, but also meet the ever-increasing requirements for performance, reliability, heat dissipation, and power distribution at a certain cost. The increase in the speed and processing capacity of functional chips requires more pins , faster clock frequency and better power distribution. At the same time, due to the increasing demand of users for ultra-thin, miniaturized, multi-functional, high-performance and low-power intelligent mobile electronic products, it directly promotes the integration of mobile terminal chip computing and communication functions, and the integration level and complexity are increasing. The higher the power consumption and the lower the cost trend. [0003] Traditional packaging techniq...

AI Technical Summary

Problems solved by technology

[0006] The purpose of the present invention is to overcome the deficiencies in the prior art, to provide a multi-layer multi-chip fan-out structure and a manufa

Images