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Reading and caching circuit and method of SRAM (Static Random Access Memory)

A technology of cache and circuit structure, applied in the field of cache circuit and SRAM reading, can solve the problems of increasing cost and consuming circuit layout area, and achieve the effect of simplifying circuit structure, reducing layout area and reducing cost

Inactive Publication Date: 2014-03-05
GUANGDONG BOGUAN TECH
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  • Summary
  • Abstract
  • Description
  • Claims
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AI Technical Summary

Problems solved by technology

Adopting this current sense amplifier structure and adding additional buffer circuits requires a larger circuit layout area and increases the cost

Method used

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  • Reading and caching circuit and method of SRAM (Static Random Access Memory)
  • Reading and caching circuit and method of SRAM (Static Random Access Memory)
  • Reading and caching circuit and method of SRAM (Static Random Access Memory)

Examples

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Embodiment Construction

[0016] Embodiments of the present invention are described in detail below.

[0017] Examples of the described embodiments are shown in the drawings, wherein like or similar reference numerals designate like or similar elements or elements having the same or similar functions throughout. The embodiments described below by referring to the figures are exemplary only for explaining the present invention and should not be construed as limiting the present invention. The following disclosure provides many different embodiments or examples for implementing different structures of the present invention. To simplify the disclosure of the present invention, components and arrangements of specific examples are described below. Of course, they are only examples and are not intended to limit the invention. Furthermore, the present invention may repeat reference numerals and / or letters in different instances. This repetition is for the purpose of simplicity and clarity and does not in i...

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Abstract

The invention provides a reading and caching circuit of an SRAM (Static Random Access Memory). The structure comprises a controllable caching device and a reading circuit, wherein the controllable caching device consists of a first PMOS (P-channel Metal Oxide Semiconductor) tube, a second PMOS tube, a first NMOS (N-channel metal oxide semiconductor) tube, a second NMOS tube and a fifth NMOS tube, and the reading circuit consists of a first PMOS tube, a second PMOS tube, a third NMOS tube, a fourth NMOS tube, a sixth NMOS tube and a seventh NMOS tube. Accordingly, the invention also provides a reading and caching method of the SRAM. Compared with the prior art, by adopting the technical scheme provided by the invention, the reading and caching circuit and the reading and caching method have the following advantages that through the method of simultaneously achieving the reading and latching of data, the layout area is reduced, the circuit structure is simplified, and the cost is reduced.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to an SRAM reading and buffering circuit and method. Background technique [0002] Flash memory (Flash Memory) is a long-life non-volatile memory (it can still maintain the stored data information in the case of power failure). Because it can still save data when the power is off, flash memory is usually used to save setting information, such as saving data in the computer's BIOS (basic input and output program), PDA (personal digital assistant), digital camera, etc. NOR Flash and NAND Flash are the two main non-volatile flash memory technologies on the market today. In the application of the Nor Flash memory chip, it is necessary to realize the reading of the page buffer memory SRAM and latch the read data at the same time. [0003] The SRAM unit generally includes two parts: a cell array and a peripheral circuit. The cell array is the core of the SRAM unit, which is compo...

Claims

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Application Information

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IPC IPC(8): G11C11/419
Inventor 张登军
Owner GUANGDONG BOGUAN TECH
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