Memory Card Access Control System Based on Programmable Logic Device

Abstract

The invention relates to a memory card access control system based on a programmable logic device. The memory card access control system comprises the programmable logic device, a storage card slot and a communication port. The programmable logic device comprises a hardware logic part and an embedded soft kernel processor. The storage card slot is electrically connected with the hardware logic part of the programmable logic device and is used for allowing a storage card to be connected in an inserting mode. The communication port is electrically connected with the hardware logic part of the programmable logic device. When the storage card is inserted in the storage card slot and works in a data transmission mode, the embedded soft kernel processor is in charge of access control of the storage card and does not conduct transmission of data written / read in the storage card with the hardware logic part. According to the memory card access control system based on the programmable logic device, the embedded soft kernel processor is in charge of access control of the storage card and does not conduct transmission of data written / read in the storage card with the hardware logic part, so that the data transmission broad width of the storage card is fully used, and the access speed of the storage card is increased. Meanwhile, the system cost can be better lowered, and the minimization of products is facilitated.

Description

technical field [0001] The invention relates to the technical field of memory card access control, in particular to a memory card access control system based on a programmable logic device. Background technique [0002] In the existing mobile memory card such as SD card access control design scheme, the system architecture has the following two schemes: 1. A microcontroller (MCU) directly accesses the SD card; 2. Access the SD card based on a microcontroller + FPGA. [0003] In actual use, the disadvantages of the above two solutions are obvious. For scheme 1, whether the SD card works in SPI (Serial Peripheral Interface, serial peripheral interface) mode or SD mode, the speed is very low, because all signal lines including clock signals are passed through GPIO (General Purpose Input Output, general purpose input / output) to operate, making it difficult for the clock signal to reach 50MHz, and the actual data transmission speed cannot reach 25MB / S. For solution 2, although ...

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Problems solved by technology

[0003] In actual use, the disadvantages of the above two schemes are obvious

For scheme 1, whether the SD card works in SPI (Serial Peripheral Interface, serial peripheral interface) mode or SD mode, the speed is very low, because all signal lines including clock signals are passed through GPIO (General Purpose Input Output, general purpose Input / Output) to operate, making it difficult for the clock signal to reach 50MHz, and the actual data transmission speed cannot reach 25MB / S.

For solution 2, although the FPGA can directly operate the SD card to ensure that the clock of the SD card reaches 50MHz, this solution has an obvious speed bottleneck, that is, the data communication rate between the microcontroller and the FPGA is low, which eventually leads to the actual SD access The speed is still well below 25MB / S

From the SD1.10 standard to the SD2.0 standard, the maximum transmission speed supported by the SD card has been increased from the original 12.5MB / S to the existing 25MB / S, but the above two solutions cannot give full play to the speed advantage of the SD card , which largely limits the scope of use of the SD card

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