Lock detector used for PLL frequency synthesizer

Abstract

The invention discloses a lock detector used for a PLL frequency synthesizer. The lock detector comprises a digital lock detector (111) and an analog lock detector (110). The digital lock detector (111) comprises a phase discrimination pulse width detector (1110), a phase discrimination pulse periodicity detector (1111), a phase inverter INV3 and a D-trigger DFF4. The two input ends of the analog lock detector (110) are connected with an UP signal and a DOWN signal which are outputted by a frequency and phase discriminator of the PLL frequency synthesizer. The analog lock detector (110) is used for outputting a phase discrimination pulse signal W1 and an analog lock detection signal ALD_output. The lock detector comprises two lock detection modes of analog and digital lock detection modes simultaneously, and "locking" and "unlocking" can be detected and precision can be configured. After a "locking" instruction, a circuit is automatically in the static state so that power consumption is reduced. Long-time counting is not needed, large-capacitance-resistance elements are not needed and the scheme is simple and easy to integrate on chips so that the lock detector is especially suitable for wireless communication application which is high in integration level and low in power consumption.

Description

technical field [0001] The present invention relates to a lock detector for use in a PLL frequency synthesizer. Background technique [0002] Lock detection is a very common and ubiquitous function in RF integrated circuits such as phase-locked loops (PLLs). For example, in low-power applications, the lock detection output of the PLL is usually used as a control signal to turn on other modules, that is, other modules are turned off when the PLL is not locked to reduce power consumption. In fast locking applications such as frequency hopping systems, the PLL lock detection output is usually used to control the dynamic loop bandwidth, that is, the PLL uses a wide loop bandwidth during the frequency acquisition process to speed up the locking process, and when it detects that it is about to lock , automatically switches to a narrow loop bandwidth to maintain good noise and spurious performance. The locking detection technology of the phase-locked loop generally includes two k...

AI Technical Summary

Problems solved by technology

The method is simple in principle and easy to integrate in the chip, but the detection accuracy is proportional to the count value. Although a larger count value can improve the detection accuracy, it makes the detection time very long

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