Fabrication method of vertical structure memory based on buried layer

A vertical structure and memory technology, applied in the field of micro-nano, can solve the problems of time-consuming and cost-consuming, and achieve the effect of superior process compatibility

Inactive Publication Date: 2017-03-29
INST OF SEMICONDUCTORS - CHINESE ACAD OF SCI
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  • Abstract
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Problems solved by technology

Compared with other processes, the etching and CMP process optimization for new materials is a relatively time-consuming and expensive process, which is also the biggest bottleneck to be faced in the verification of new storage materials

Method used

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  • Fabrication method of vertical structure memory based on buried layer
  • Fabrication method of vertical structure memory based on buried layer
  • Fabrication method of vertical structure memory based on buried layer

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Embodiment Construction

[0020] In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be further described in detail below in conjunction with specific embodiments and with reference to the accompanying drawings.

[0021] figure 1 A flow chart of a method for fabricating a buried layer-based vertical structure memory proposed by the present invention is shown. Figure 2A - Figure 2k shows a schematic diagram of the manufacturing process of the buried layer-based vertical structure memory proposed by the present invention. see figure 1 , Figure 2A --As shown in Figure 2k, the present invention provides a method for preparing a buried layer-based vertical structure memory, the method comprising:

[0022] Step 1: On the substrate 101, deposit an electrothermal insulating material layer 102 and a sacrificial material layer 103 in sequence, such as Figure 2A shown;

[0023] The material of the substrate 101 can be silicon, gallium...

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Abstract

The invention discloses a method for preparing a storage of a vertical structure on the basis of a buried layer. According to the method, a bottom electrode is buried, a function material layer is stored, and accordingly good electric heating insulation is achieved, and the situation that a CMP is relied on when a component of a vertical structure is prepared in the prior art is eliminated. According to the method, under the assistance of high-precision linear photoetching means such as electron beam lithography and focused particle beam etching and high-precision thin-film deposition and etching processes, the defects that the development cycle is long, development is difficult, cost is high and adaptability is poor due to development bottlenecks of a CMP technique are solved in development of the vertical structure in the prior art, and the method has great advantages in preparation precision, preparation efficiency, economical performance, compatibility with an existing CMOS process and the like.

Description

technical field [0001] The invention relates to the field of micro-nano technology, in particular to a method for preparing a buried layer-based vertical structure memory. Background technique [0002] The accelerated development of high-tech industries and basic service facilities has higher and higher requirements for fast computing and efficient storage, and the improvement of CPU processing capabilities is increasingly dependent on the speed and power consumption of memory chips. Therefore, how to develop efficient storage It will become one of the key technologies that urgently need a breakthrough in the future. Phase change memory PCRAM (phase change random access memory) is non-volatile. Compared with most current memories, it has the advantages of small device size, low power consumption, fast reading speed, radiation resistance, multi-level storage and compatibility with current Some CMOS process compatibility and many other advantages. With a similar device struc...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L45/00
Inventor 付英春王晓峰杨富华
Owner INST OF SEMICONDUCTORS - CHINESE ACAD OF SCI
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