Manufacturing method for semiconductor device

A manufacturing method and semiconductor technology, applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., can solve problems such as low production efficiency, complicated manufacturing process, and complicated manufacturing technology, and achieve the effect of accurate dimensions

Active Publication Date: 2014-05-14
SEMICON MFG INT (SHANGHAI) CORP
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Problems solved by technology

Moreover, the cell array area is completed before the peripheral circuit area, but the manufacturing process is more complicated, and it is necessary to sequentially deposit an uncertain carbon film (APF), a dielectric anti-reflection layer (DARC), APF, DARC, and bottom anti-reflection on the surface of the multilayer deposition film. Layer and p

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  • Manufacturing method for semiconductor device
  • Manufacturing method for semiconductor device
  • Manufacturing method for semiconductor device

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[0026] In order to make the objectives, technical solutions and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments.

[0027] The schematic flow chart of the manufacturing method of the semiconductor device of the present invention is as figure 1 As shown, it includes the following steps, which are combined below Figure 2a to Figure 2i Be explained.

[0028] Step 11. Please refer to Figure 2a , A semiconductor substrate 100 with a multilayer deposited film is provided in advance, a first bottom anti-reflection layer 101 and a first patterned photoresist layer 102 are sequentially formed on the surface of the deposited film, and the first patterned light The resist layer 102 defines the active area of ​​the peripheral circuit;

[0029] Among them, the multilayer deposited film sequentially includes a gate oxide layer (GOX), a polysilicon layer (poly), a silicon nitrid...

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Abstract

The invention discloses a manufacturing method for a semiconductor device. A semiconductor substrate having multiple deposited films is provided in advance, a first bottom antireflective layer and a first patterning photo-resistive glue layer are formed at a surface of the deposited films, and the first patterning photo-resistive glue layer defines an active region of a peripheral circuit; the first patterning photo-resistive glue layer is taken as a mask, and the semiconductor substrate is etched to a predetermined depth to form a groove; after the first bottom antireflective layer and the first patterning photo-resistive glue layer are removed, first oxidation layers are deposited in the groove and the surface of the deposited films; APF, DARC, a second bottom antireflective layer and a second patterning photo-resistive glue layer are formed at surfaces of the first oxidation layers, and the second patterning photo-resistive glue layer defines an active region of a unit array; the second patterning photo-resistive glue layer is taken as a mask, and APF is etched; the APF is taken as a sacrificial layer employing an SADP method to form an oxidation line having a predetermined width; the oxidation line is etched to the predetermined depth of the semiconductor substrate. The manufacturing method has the simplified technology.

Description

technical field [0001] The invention relates to a manufacturing technology of a semiconductor device, in particular to a manufacturing method of a semiconductor device. Background technique [0002] At present, a memory device includes a peripheral circuit area and a cell array area, and a self-aligned double patterning (SADP, Self-Aligned Double Patterning) technology is generally used to form the cell array area of ​​the memory device. Moreover, the cell array area is completed before the peripheral circuit area, but the manufacturing process is more complicated, and it is necessary to sequentially deposit an uncertain carbon film (APF), a dielectric anti-reflection layer (DARC), APF, DARC, and bottom anti-reflection on the surface of the multilayer deposition film. Layer and photoresist layer, etc., successively make the cell array area and the peripheral circuit area, and the multi-layer deposited film on the semiconductor substrate includes gate oxide layer (GOX), polys...

Claims

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Application Information

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IPC IPC(8): H01L21/822H01L21/308H01L21/311
CPCH01L21/3086H01L21/3088H01L21/31105
Inventor 周朝礼
Owner SEMICON MFG INT (SHANGHAI) CORP
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