Manufacturing method for semiconductor device

Abstract

The invention discloses a manufacturing method for a semiconductor device. A semiconductor substrate having multiple deposited films is provided in advance, a first bottom antireflective layer and a first patterning photo-resistive glue layer are formed at a surface of the deposited films, and the first patterning photo-resistive glue layer defines an active region of a peripheral circuit; the first patterning photo-resistive glue layer is taken as a mask, and the semiconductor substrate is etched to a predetermined depth to form a groove; after the first bottom antireflective layer and the first patterning photo-resistive glue layer are removed, first oxidation layers are deposited in the groove and the surface of the deposited films; APF, DARC, a second bottom antireflective layer and a second patterning photo-resistive glue layer are formed at surfaces of the first oxidation layers, and the second patterning photo-resistive glue layer defines an active region of a unit array; the second patterning photo-resistive glue layer is taken as a mask, and APF is etched; the APF is taken as a sacrificial layer employing an SADP method to form an oxidation line having a predetermined width; the oxidation line is etched to the predetermined depth of the semiconductor substrate. The manufacturing method has the simplified technology.

Description

technical field [0001] The invention relates to a manufacturing technology of a semiconductor device, in particular to a manufacturing method of a semiconductor device. Background technique [0002] At present, a memory device includes a peripheral circuit area and a cell array area, and a self-aligned double patterning (SADP, Self-Aligned Double Patterning) technology is generally used to form the cell array area of ​​the memory device. Moreover, the cell array area is completed before the peripheral circuit area, but the manufacturing process is more complicated, and it is necessary to sequentially deposit an uncertain carbon film (APF), a dielectric anti-reflection layer (DARC), APF, DARC, and bottom anti-reflection on the surface of the multilayer deposition film. Layer and photoresist layer, etc., successively make the cell array area and the peripheral circuit area, and the multi-layer deposited film on the semiconductor substrate includes gate oxide layer (GOX), polys...

AI Technical Summary

Problems solved by technology

Moreover, the cell array area is completed before the peripheral circuit area, but the manufacturing process is more complicated, and it is necessary to sequentially deposit an uncertain carbon film (APF), a dielectric anti-reflection layer (DARC), APF, DARC, and bottom anti-reflection on the surface of the multilayer deposition film. Layer and photoresist layer, etc., successively make the cell array area and peripheral circuit area, and the multi-layer deposited film includes gate oxide layer (GOX), polysilicon layer (poly), silicon nitride layer (SiN) and Pad Oxide (OX)

The existing production technology is relatively complicated, and the production efficiency is low when it is realized

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