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Programmable Built In Self Test (pBIST) system

A technology of embedded memory and test system, applied in the field of built-in self-test system, can solve problems such as insufficient influence and unobservable

Active Publication Date: 2014-06-18
TEXAS INSTR INC
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  • Application Information

AI Technical Summary

Problems solved by technology

Manufacturing defects will generally affect all parts manufactured
These techniques have several limitations
The main limitation is interfacing with the CPU which functions in mostly inaccessible memory
Inability to do back-to-back access to all memory is another severe limitation
Third, direct memory access (DMA) external memory access cannot be achieved at full processor speed during memory testing while the device is in wafer form
This can result in failure to observe a significant number of

Method used

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Embodiment Construction

[0014] The SRAM / memory structure of different devices varies by technology, design and implementation. In order to effectively test a memory, the memory test algorithm's sequence of address access patterns should follow a specific pattern that sensitizes and tests electrical structures within the memory.

[0015] In simple memory structures, physical addresses and logical addresses are contiguous and match. Efficient testing can be performed with a simple algorithm that increments or decrements addresses linearly. In these memories, any possible address scrambling automatically matches the input with the output. That is, bit of the input becomes bit of the output, and so on.

[0016] FIG. 1 illustrates a representative prior art integrated circuit (IC): a system-on-chip (SOC) device 100 including a programmable built-in self-test (pBIST) 130 .

[0017] SOC device 100 contains multiple modules that can be very complex to test. SOC 100 includes central processing unit (CPU...

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Abstract

A programmable Built In Self Test (pBIST) system used to test embedded memories where a plurality of memories requiring different testing conditions are incorporated in an SOC. The pBIST Read Only Memory storing the test setup data is organized to eliminate multiple instances of test setup data for similar embedded memories.

Description

technical field [0001] The technical field of the invention is high speed memory testing, and more particularly, a built-in self-test (BIST) system for embedded memories. Background technique [0002] Testing fabricated integrated circuits to determine proper operation has always been a challenging task, especially with regard to on-board memory functionality. There are two main types of device failures caused by design flaws. Design defects occur when integrated circuits are manufactured to design specifications that do not provide proper function for the intended use. This defect affects any integrated circuit manufactured until the design defect is corrected. Integrated circuit manufacturers must detect and correct such defects before shipping large numbers of devices to customers to avoid costly recalls. In contrast to design defects, manufacturing defects involve some failure in the manufacture of integrated circuits. A manufacturing defect will generally affect not...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C29/12
CPCG01R31/318555G01R31/318519G11C29/16G11C2029/0401G11C29/36G11C29/12G11C17/00
Inventor 拉古拉姆·达莫达兰纳韦恩·布霍里亚阿曼·科克拉迪
Owner TEXAS INSTR INC
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