Time-sequence control circuit of static random access memory (SRAM)
A static random access, timing control circuit technology, applied in static memory, digital memory information, information storage and other directions, can solve problems such as reducing stability, and achieve the effect of easy implementation, small area and simple structure
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[0023] In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be described in further detail below in conjunction with specific embodiments and with reference to the accompanying drawings.
[0024] The read and write operations of SRAM depend on the cooperation between each functional module. figure 1 It is a schematic diagram of the overall structure of the existing SRAM, which includes a decoding circuit, a cell array, a sense amplifier and a timing control circuit. The timing control circuit is used to receive external clock signals and control signals, and generate timing control signals required for the internal functional modules to work. The signal 002 is the enabling signal of the pre-charging circuit, which is used to control when the pre-charging circuit is turned on or off. The signal 003 is the enabling signal of the decoding circuit, which is used to control when the decoding circuit is turned o...
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