Method for manufacturing MOS device capable of reducing negative bias temperature instability

Abstract

A method for manufacturing a MOS device capable of reducing negative bias temperature instability sequentially comprises the following steps of performing trap injecting on a substrate to form a P type trap and an N type trap, manufacturing a grid electrode oxidation layer on the surface of the substrate, depositing a grid electrode layer on the surface of the grid electrode oxidation layer, performing photoetching on the grid electrode layer to form a PMOS grid electrode on the P type trap, and form an NMOS grid electrode on the N type trap, depositing a first silicon nitride thin film on the surface of a silicon wafer, utilizing UV light for irradiating the silicon wafer, manufacturing first grid electrode side walls on the side edge of the PMOS grid electrode and the side edge of the NMOS grid electrode respectively, performing light-dope injecting to form a PMOS light-dope source drain structure in the P type trap, and form an NMOS light-dope source drain structure in the N type trap, depositing a silicon nitride thin film on the surface of the device, manufacturing a second side wall on one side edge of each grid electrode side wall, performing injection forming on source drain, and therefore forming a PMOS source drain electrode in the P type trap, and forming an NMOS source drain electrode in the N type trap.

Description

technical field [0001] The present invention relates to the field of semiconductor manufacturing, and more specifically, the present invention relates to a CMOS device manufacturing method for reducing negative bias temperature instability (NBTI: Negative Bias Temperature Instability). Background technique [0002] With the rapid development of VLSI technology, the size of MOSFET devices is constantly decreasing. Due to the drastic reduction in the size of MOSFET transistors, the thickness of the gate oxide layer has been reduced to 2nm or even thinner. While the size of the MOS device is scaled down, the operating voltage is not proportionally reduced, which makes the channel electric field and the oxide layer electric field of the MOS device significantly increased, and the degradation caused by the NBTI effect is becoming more and more significant. NBTI, that is, negative bias temperature instability, usually refers to the performance degradation of PMOS transistors unde...

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Problems solved by technology

However, due to the presence of hydrogen in many processes such as film deposition, etching, ion implantation, and cleaning during the fabrication of devices, these hydrogens will diffuse into SiO2 driven by the thermal budget. 2 / Si interface, combined with Si dangling bonds to form Si-H bonds, thus intensifying the NBTI effect

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