Manufacturing method of CMOS (Complementary Metal-Oxide-Semiconductor Transistor) device for reducing back bias voltage and temperature instability

Abstract

The invention provides a manufacturing method of a CMOS (Complementary Metal-Oxide-Semiconductor Transistor) device for reducing back bias voltage and temperature instability. The manufacturing method comprises the following steps: step 1, carrying out trap injection in a substrate to form a P type trap and an N type trap; step 2, manufacturing a grid electrode oxidized layer on the surface of the substrate; step 3, depositing a grid electrode layer on the surface of the grid electrode oxidized layer; step 4, carrying out photo-etching on the grid electrode layer to form a PMOS (P-channel Metal Oxide Semiconductor) grid electrode on the P type trap; forming an NMOS (N-channel Metal Oxide Semiconductor) grid electrode on the N type trap; step 5, respectively manufacturing grid electrode side walls I at the side edges of the PMOS grid electrode and the NMOS grid electrodes; step 6, carrying out light dope injection to form a PMOS light dope source drain structure and forming an NMOS light dope source drain structure in the N type trap; step 7, depositing a silicon nitride thin film on the surface of the device; step 8, irradiating on a silicon wafer by using UV (Ultraviolet) light; step 9, manufacturing a side wall II at one side edge of each grid electrode side wall I; and step 10, carrying out source drain injection formation so as to form a PMOS source drain electrode in the P type trap and form an NMOS source drain electrode in the P type trap.

Description

technical field [0001] The present invention relates to the field of semiconductor manufacturing, and more specifically, the present invention relates to a CMOS device manufacturing method for reducing negative bias temperature instability (NBTI: Negative Bias Temperature Instability). Background technique [0002] With the rapid development of VLSI technology, the size of MOSFET devices is constantly decreasing. Due to the drastic reduction in the size of MOSFET transistors, the thickness of the gate oxide layer has been reduced to 2nm or even thinner. While the size of the MOS device is scaled down, the operating voltage is not proportionally reduced, which makes the channel electric field and the oxide layer electric field of the MOS device significantly increased, and the degradation caused by the NBTI effect is becoming more and more significant. NBTI, that is, negative bias temperature instability, usually refers to the performance degradation of PMOS transistors unde...

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Problems solved by technology

However, due to the presence of hydrogen in many processes such as film deposition, etching, ion implantation, and cleaning during the fabrication of devices, these hydrogens will diffuse into SiO2 driven by the thermal budget. 2 / Si interface, combined with Si dangling bonds to form Si-H bonds, thus intensifying the NBTI effect

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