Graphene-based hot-electron transistor based on ALD (atomic layer deposition) and preparation method of graphene-based hot-electron transistor

Abstract

The invention provides a graphene-based hot-electron transistor based on ALD (atomic layer deposition) and a preparation method of the graphene-based hot-electron transistor. The preparation method comprises the following steps: (1) providing heavy doping N-type Si and growing emitter region electrodes at both sides of the surface of the Si; (2) carrying out thermal oxidation on the surface of the heavy doping N-type Si to form a first potential barrier; (3) forming a single graphitic layer on the surface of the first potential barrier as a base region and forming base region electrodes at both sides of the surface of the single graphitic layer; and (4) forming a second potential barrier between the base region electrodes on the surface of single-layer graphene by utilizing an ALD process and forming a metal collector region on the surface of the second potential barrier. By adopting the preparation method, the performance of a hot-electron device is relatively good by preparing the single graphene layer as the base region, utilizing the performance of quasi ballistic transport of the graphene and combining tunneling characters of hot-electron, and the potential barrier of high-k metallic oxide grown on the surface of the single-layer graphene by utilizing the ALD is controllable in thickness, free of pinhole and good in quality. In addition, the preparation method provided by the invention is accurate in preparation, simple and high in yield.

Description

technical field [0001] The invention relates to the field of semiconductor device manufacturing, and relates to a thermal electron transistor and a preparation method thereof, in particular to an ALD-based graphene-based thermal electron transistor and a preparation method thereof. Background technique [0002] According to Moore's Law, the integration level of chips doubles every 18 months to 2 years, that is, the processing line width is reduced by half. The development path of extending Moore's Law by using silicon-based semiconductor materials with decreasing dimensions (the processing limit of silicon materials is generally considered to be 10 nanometer line width) is gradually approaching the end. With the continuous reduction of device size in the field of microelectronics, silicon material is gradually approaching its processing limit. In order to prolong the life of Moore's Law, the international semiconductor industry has proposed beyond silicon technology (Beyond...

AI Technical Summary

Problems solved by technology

[0006] In view of the above-mentioned shortcomings of the prior art, the object of the present invention is to provide an ALD-based graphene-based thermionic transistor and its p

Images