Mixed interconnection Mesh topological structure for on-chip network and routing algorithm thereof

Abstract

The invention provides a mixed interconnection Mesh topological structure for an on-chip network and a routing algorithm of the mixed interconnection Mesh topological structure. Path conditions are preset for data packages; whether data in a buffer area of an input port of a next-level routing node exceed a preset proportional value is judged through a current routing node according to a preset path firstly, and if the data do not exceed the preset proportional value, the data are transmitted along a path selected in advance; if the data exceed the preset proportional value and the storage content of buffer area data of corresponding input ports of two adjacent routing nodes meeting the requirements of the minimum path is not full, the routing node corresponding to fewer buffer area data packages of the input port is selected as a next-level routing node; if the buffer areas of the corresponding input ports are all full, transmission is carried out by sharing bus. Due to the fact that an HPA routing algorithm can be transmitted through a bus during network congestion, the deadlock phenomenon cannot occur; because the routing algorithm belongs to minimum path algorithms, the livelock phenomenon cannot occur; the data packages of all nodes are equally positional in the transmission process, and the starvation phenomenon cannot occur.

Description

technical field [0001] The invention relates to a hybrid interconnection Mesh topology structure and routing algorithm for on-chip networks. Background technique [0002] The topology of the network on chip defines the physical layout of the distribution and connection of various modules in the network on the chip. The choice of topology will directly affect the network node degree, network diameter, and network scale, thereby affecting network delay, throughput, energy consumption, area, and fault tolerance, and ultimately has an important impact on network performance parameters. Therefore, in the network on a chip, the research on the design of the topology is one of the focuses of the current research. [0003] Several regular topologies commonly used in on-chip network design are as follows: [0004] 1. Two-dimensional grid structure (2D Mesh) [0005] The two-dimensional grid structure is a regular structure, and it is the most commonly used, simple and intuitive to...

AI Technical Summary

Problems solved by technology

The disadvantages of this structural design are: symmetry can easily cause congestion and hotspots in the central area, resulting in unbalanced network load distribution; its edge nodes are relatively blocked, and long-distance multi-hop communication between remote nodes can easily cause excessive delay; bandwidth, delay, etc. The performance in terms of performance is not optimal; for networks with high requirements for real-time data transmission, in this case, the quality of service (Quality of Service, QoS) cannot be guaranteed

However, since the adaptive routing algorithm needs real-time monitoring, calculation, feedback, and decision-making during the implementation process, the implementation complexity is relatively high

In addition, since the routing path is uncertain, the adaptive routing algorithm may have a deadlock problem

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