IP core based on JESD 204 protocol

Abstract

The invention provides an IP core based on the JESD204 protocol and aims to provide an IP core which is strong in anti-interference capability high in transmission rate and unaffected by inter symbol interference and synchronous influence. The IP core based on JESD204 protocol is realized by adopting the following technical proposal; FPGA ( Field Programmable Gate Array) contains multiple GTX interfaces; each GTX interface receives data conforming to the JESD 204 protocol through a pair of differential signaling wires between an analog-digital converter ADC chip and each GTX interface in a serial manner; the IP core based on the JESD 204 protocol is characterized in that a clock generation unit generates all the input clocks required by all the other functional units; a reset function unit logically controls and generates reset signals, so as to receive control signals generated by a control state machine; a physical layer calls a high-speed serial transceiver inside the FPGA, so as to send converted parallel data to a data error detection function unit; the parallel data is further sent to a K code detection function unit for K code detection; the detected k code is sent to a K code count function unit for counting; a link synchronization function unit judges the synchronous state of a high-speed serial transmission link according to the detection results of the K code detection function unit; a data delay function unit conducts a delay treatment on the data from the GTX and provides the delay processed data for a K code substitution function unit.

Description

technical field [0001] The invention relates to an IP core capable of realizing the AD sampling data serial transmission protocol JESD204 protocol. Background technique [0002] AD sampling technology is widely used in aviation, aerospace and ground communication equipment. When the communication terminal captures information in a specific frequency band (such as Ka / Ku frequency band, U / V frequency band, etc.), it is necessary to complete the second down-conversion of the received data to restore output digital baseband data. The first down-conversion is realized in the channel module of the communication terminal (usually the frequency is converted from GHz to MHz); the second down-conversion is to convert the MHz-level analog signal into a digital signal through high-speed AD sampling technology, and then complete the demodulation. When sampling data is transmitted, parallel transmission is usually used, that is, the sampling data is transmitted through multi-bit data lin...

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Problems solved by technology

[0003] 1. Since the data is transmitted in parallel, there must be crosstalk and synchronization problems between codes in parallel transmission. Therefore, the sampling frequency of the analog-to-digital converter ADC chip in the parallel transmission mode is usually not higher than 100MHz. The current mature AD9244 has the highest sampling frequency. It is also only 65MHz, which cannot meet some applications that require high-precision analog-to-digital converter ADCs, such as SAR radar and broadband links;

[0004] 2. When data is transmitted in parallel, a large number of signal lines are required. Therefore, the parallel analog-to-digital converter ADC chip is usually single-channel. If multi-channel AD sampling is required, multiple analog-to-digital converter ADC chips can only be stacked. , with large area and volume, it is not suitable for application in space-constrained aerospace airborne and spaceborne environments

However, the JESD204 protocol has not yet been implemented in China (verified through literature search), and it is only mastered by a few foreign companies, and it is provided to domestic customers at a high price through netlist files (ngc files), which increases the number of engineering projects. Development costs are not conducive to technology upgrades

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