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Method for improving accuracy of light doping drain electrode injection position

A lightly doped drain, accurate technology, applied in electrical components, semiconductor/solid-state device manufacturing, circuits, etc., can solve problems such as device leakage problems

Inactive Publication Date: 2014-10-01
CSMC TECH FAB2 CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0005] Based on this, in order to solve the device leakage problem caused by alignment offset, it is necessary to provide a method to improve the accuracy of the lightly doped drain implantation position

Method used

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  • Method for improving accuracy of light doping drain electrode injection position
  • Method for improving accuracy of light doping drain electrode injection position
  • Method for improving accuracy of light doping drain electrode injection position

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Embodiment Construction

[0018] In order to make the objects, features and advantages of the present invention more comprehensible, specific implementations of the present invention will be described in detail below in conjunction with the accompanying drawings.

[0019] figure 2 It is a flow chart of a method for improving the accuracy of the lightly doped drain implant position in an embodiment, including the following steps:

[0020] S10, deposit polysilicon on the wafer.

[0021] Polysilicon is deposited on the wafer with gate oxide and shallow trench isolation (STI) structures for the high voltage device regions.

[0022] S20, coating photoresist on the polysilicon, using a first photolithography mask to expose and develop, and then etching the polysilicon to form a first gate.

[0023] After coating the photoresist, the photoresist is exposed and developed with the photoresist mask plate of the gate of the high voltage device area, and then the polysilicon is etched to form the gate of the hi...

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Abstract

The invention discloses a method for improving accuracy of the light doping drain electrode injection position. The method includes the following steps that polycrystalline silicon is settled on a wafer; the polycrystalline silicon is coated with photoresist and is etched after being exposed and developed through a first photoetching mask template, so that a first grid electrode is formed; light doping drain electrode ion injection of a first device region is conducted on the wafer; the photoresist is removed. According to the method, relative offset can not be generated between the grid electrode of the high-voltage device region and an LDD injection pattern of the high-voltage device region, so that accuracy of the light doping drain electrode injection position is improved.

Description

technical field [0001] The invention relates to a manufacturing method of a semiconductor device, in particular to a method for improving the accuracy of lightly doped drain injection position. Background technique [0002] The lightly doped drain (LV LDD) ion implantation of the low-voltage device region of traditional logic devices is generally carried out after the formation of the polysilicon gate. With the help of the barrier effect of the etched polysilicon (POLY) pattern, the conductive particles are implanted into the polysilicon-free In the blocked active area (ie, the source and drain area), the conductive particles in the polysilicon area are blocked by the polysilicon and will not be injected into the underlying silicon substrate. [0003] However, for the high-voltage device area, high-voltage lightly doped drain (HV LDD) implantation is required. The implantation energy is large and can penetrate polysilicon. Therefore, the polysilicon gate is generally formed ...

Claims

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Application Information

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IPC IPC(8): H01L21/266H01L21/8234
CPCH01L21/266H01L29/0882
Inventor 李健
Owner CSMC TECH FAB2 CO LTD