cmp process simulation method and its simulation system
A process simulation and process technology, applied in software simulation/interpretation/simulation, instrumentation, calculation, etc., can solve problems such as large amount of data, high computational cost, inability to apply chip-level and silicon-wafer-level CMP process simulation processes, etc. High accuracy, reduced computational complexity, and reduced R&D costs
Active Publication Date: 2017-08-11
INST OF MICROELECTRONICS CHINESE ACAD OF SCI
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Problems solved by technology
However, this graphics-level CMP process simulation system has a huge amount of data and high calculation costs during the chip layout CMP process simulation process, and cannot be applied to existing functions even with the super processing capabilities of existing computing clusters. Complete and highly integrated processing chip analysis process, so that it cannot be applied to the existing chip-level and silicon-level CMP process simulation process
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[0064] As mentioned in the background technology section, providing a fast and effective CMP process simulation method and its simulation system that can meet the requirements of correctly predicting the chip surface morphology after the CMP process has become an urgent problem to be solved in the field of semiconductor processing technology and process modeling question.
[0065] The inventor has found that, when the CMP process simulation method in the prior art performs CMP process simulation on the physical layout of the whole chip, no matter which CMP process simulation system is used, and no matter whether the serial mode or the parallel mode is adopted, the chip will be processed every time. In the process of layout simulation, it is necessary to make detailed simulation calculations for each tiny area in the specific chip layout, resulting in relatively high computational complexity, which leads to low simulation efficiency of the CMP process simulation system. Moreover...
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The embodiment of the present invention discloses a CMP process simulation method and a simulation system. The method includes: performing grid division on the chip layout, forming a plurality of grid units, and extracting the graphic features of each grid unit; The graphic features of each grid unit are index targets, and in the preset multi-dimensional spatial data table, search for the CMP process simulation surface topography data corresponding to the graphic features of each grid unit, and obtain the CMP process simulation results of each grid unit; for each grid unit The CMP process simulation results of grid cells are summarized to obtain the CMP process simulation results of the chip layout; wherein, the preset multi-dimensional spatial data table includes graphic features that determine the surface topography of the CMP process and a graphic-level CMP process simulation surface A multi-dimensional spatial data table of the corresponding relation of topography data. Therefore, the computational complexity of performing CMP process simulation on the chip layout is reduced, and the research and development cost is also reduced.
Description
technical field [0001] The invention relates to the technical field of chemical mechanical polishing, in particular to a CMP process simulation method and a simulation system thereof. Background technique [0002] Chemical Mechanical Polishing (CMP, Chemical Mechanical Polishing) is the most widely used and most effective global planarization process in the current integrated circuit manufacturing technology, especially in the copper back-end interconnection process. The CMP process generally includes multiple steps such as chemical reaction and physical removal. It is a complex process in which various factors such as the size of the abrasive particle, the property of the polishing pad, the composition of the polishing liquid, the downforce, and the relative speed between the polishing pad and the wafer interact and interact. [0003] With the advancement of semiconductor processing technology, the complexity of nanoscale chip design has increased significantly. Chip) two ...
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IPC IPC(8): G06F17/50G06F9/455
Inventor 刘宏伟陈岚方晶晶孙艳张贺马天宇
Owner INST OF MICROELECTRONICS CHINESE ACAD OF SCI