Semiconductor device and manufacturing process method thereof

Abstract

The invention discloses a semiconductor device. An epitaxial layer is deposited on a substrate; a P well is formed on the epitaxial layer; an N+ source region is encircled in the P well; at least a part of the P well is provided with a gate oxide and a grid electrode; the upper portion of the epitaxial layer is provided with an N- drift region and an N+ drift region, wherein the N- drift region is arranged between the grid electrode and an N+ drain region and is tightly close to the grid electrode; the grid electrode is formed through a self-aligning process; the top of the grid electrode helps to reduce the resistance of the grid electrode through groove metal; metal silicide can be formed on the N+ drain region; the N+ drain region is connected with metal wires of a top layer through a contact hole and a through hole; the N+ source region is connected with the P well surrounding the N+ source region through metal connection or the metal silicide; and the P well is connected with the substrate through a metal plug passing through the epitaxial layer. The invention also discloses a manufacturing process method of the semiconductor device. The iron injection of the N- drift region and the preparation of the shield grid are done before the formation of the grid electrode. The defects of the N- drift region can be reduced, and the stability and reliability of the device can be improved.

Description

technical field [0001] The invention relates to the field of semiconductor integrated circuits, in particular to a semiconductor device. The invention also relates to a manufacturing process method of the semiconductor device. Background technique [0002] Radio Frequency Laterally Diffused Metal-Oxide Semiconductor (RFLDMOS) is a device with good market demand. Especially with the wide application of communication technology, it will get more and more attention as a new type of power device. [0003] The basic structure of existing RFLDMOS such as figure 1 shown. Generally, a P+ substrate 1 doped with high-concentration P-type impurities (resistivity 0.01-0.02 ohm.cm) is used, and P- epitaxial layers 2 of different thicknesses and doping concentrations are grown on it according to the requirements of the withstand voltage of the device (such as resistance The voltage is 60 volts, the thickness is about 5-8 microns), and the P+ sinker layer (P+SINKER) 10 is formed by imp...

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Problems solved by technology

[0005] In the above process method, since the LDD implantation is performed after the polysilicon gate is formed, the shield gate dielectric film 8 and the shield gate 29 are completed after the polysilicon gate and the LDD are formed, so processes such as LDD implantation and shield gate 29 etching are carried out During the process, some damage may be formed on the silicon-SiO2 (silicon dioxide) interface, and at the same time, residual charges may be formed in the dielectric film in this area during the implantation and etching process, which will have a negative impact on the performance and reliability of the device. In addition, since the wells of the device have been formed before the etching process of the shielding gate 29, there will be no long-term high-temperature thermal process after the etching of the shielding gate to repair the defects caused by etching

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