Fabrication Process of Superjunction Devices
A preparation process and super junction device technology, applied in the field of super junction device preparation process, can solve the problems of N/P charge imbalance breakdown voltage, difficult to realize, narrow bottom, etc., to reduce the difficulty of filling and the formation of defects, The effect of optimizing device characteristics and improving breakdown voltage
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Embodiment 1
[0038] Step S1: Provide a substrate 10, grow multiple epitaxial layers with the first conductivity type sequentially from bottom to top on the top of the substrate 10, and after forming each epitaxial layer, etch the epitaxial layer to form several spaced apart trenches, and then filling the trenches with a semiconductor layer of the second conductivity type, wherein the trenches formed in any two upper and lower adjacent epitaxial layers correspond to each other and overlap up and down.
[0039] In this embodiment, the above-mentioned first conductivity type is an N-type conductivity type, and the second conductivity type is a P-type conductivity type.
[0040] In the present invention, firstly, a first layer of epitaxial layer (N-type conductivity type) 11 with a thicker thickness and lower doping is formed on a substrate 10 provided by an epitaxial growth process, and then through a substrate with an opening The patterned mask layer etches the first epitaxial layer 11 to fo...
Embodiment 2
[0051] Step S1: Provide a substrate 50, first deposit a buffer layer 51 with the second conductivity type on the upper surface of the substrate 50, and then grow multiple layers of the first conductivity type sequentially on the buffer layer 51 from bottom to top. epitaxial layer, and after each epitaxial layer is formed, the epitaxial layer is etched to form a plurality of spaced apart trenches 60, and then the trenches 60 are filled with a semiconductor layer of the second conductivity type, wherein any The trenches formed in the epitaxial layers adjacent to each other up and down correspond to each other and overlap up and down.
[0052] In this embodiment, the above-mentioned first conductivity type is a P-type conductivity type, and the second conductivity type is an N-type conductivity type.
[0053] Specifically, an N-type buffer layer 51 is first formed on the substrate 50, and then a first layer of epitaxial layer 52 with P-type heavy doping is sequentially deposited ...
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