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Packaging method for board level fan-out structures

A packaging method and fan-out technology, applied in semiconductor devices, electrical components, circuits, etc., can solve the problems of mechanical warpage manufacturing efficiency of board-level fan-out structure, low board-level fan-out structure, etc., to ensure quality and performance, the effect of improving production efficiency

Active Publication Date: 2014-12-24
北京中科微投资管理有限责任公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] The technical problem to be solved by the present invention is to provide a packaging method for board-level fan-out structures that can solve the problem of easy mechanical warpage in the manufacturing process of board-level fan-out structures and low manufacturing efficiency

Method used

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  • Packaging method for board level fan-out structures
  • Packaging method for board level fan-out structures
  • Packaging method for board level fan-out structures

Examples

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Embodiment Construction

[0029] see figure 1 , an embodiment of the present invention provides a packaging method for a board-level fan-out structure, including:

[0030] Step 1: See figure 1 , press the first double-layer copper foil 2 on the upper side of the core board 1 (using prepreg or double-sided copper-clad organic substrate), and press the second double-layer copper foil 3 on the lower side of the core board 1; The layer copper foil 2 and the second double-layer copper foil 3 are peelable structures. The thickness of the outer layer copper foil in the first double layer copper foil 2 is greater than the thickness of the inner layer copper foil; the thickness of the outer layer copper foil in the second double layer copper foil 3 is greater than the thickness of the inner layer copper foil.

[0031] Step 2: See figure 2 The first chip 4 is mounted on the outside of the first double-layer copper foil 2, the second chip 5 is mounted on the outside of the second double-layer copper foil 3, a...

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Abstract

The invention relates to the technical field of electronic packaging, in particular to a packaging method for board level fan-out structures. The method includes the steps of copper foil pressing fit, chip surface mounting, medium layer pressing fit, blind hole manufacturing, circuit manufacturing, installed and welded layer pressing fit, ball attachment, stripping and others. According to the packaging method for the board level fan-out structure, two fan-out packaging structures are symmetrically designed on the upper side and the lower side of a core board, and in the manufacturing process, because the upper end and the lower end of the core board are symmetrically and evenly stressed, and a high-temperature annealing mode is adopted for eliminating internal stress before a first double-layer copper foil structure and a second double-layer copper foil structure are stripped, the problem of warping and other mechanical deformation problems will not occur, and the quality and performance of the fan-out structures are guaranteed. In addition, the packaging method for the board level fan-out structures can be used for manufacturing the two fan-out structures at the same time, and therefore production efficiency is improved.

Description

technical field [0001] The invention relates to the technical field of electronic packaging, in particular to a packaging method of a board-level fan-out structure. Background technique [0002] Electronic high-density packaging is widely valued by the industry. The three-dimensional stacking of chips effectively reduces the three-dimensional size of the device, and the stacking method between chips is also continuously improved. From Flip Chip to silicon-based TSV (Through Silicon Via) through-hole interconnection technology, the three-dimensional size of devices has become smaller and smaller. The packaging process has also evolved from the original bonding, patch, and plastic packaging to key process technologies such as RDL, Flip Chip, wafer bonding, and TSV introduced in the front-end process, making packaging structures with higher chip density and smaller size continue to emerge. During the manufacturing process of the existing fan-out structure, problems such as w...

Claims

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Application Information

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IPC IPC(8): H01L21/60H01L21/58
CPCH01L21/6835H01L2221/68386
Inventor 郭学平
Owner 北京中科微投资管理有限责任公司
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