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Manufacturing method of semiconductor device shallow-trench isolation structure

A technology of isolation structure and manufacturing method, which is applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., can solve the problems that the STI isolation structure is difficult to further shrink and affect device performance, etc., to reduce width, increase area, and improve integration degree of effect

Active Publication Date: 2015-01-14
SEMICON MFG INT (SHANGHAI) CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0010] In view of the above-mentioned shortcomings of the prior art, the object of the present invention is to provide a method for manufacturing a shallow trench isolation structure of a semiconductor device, which is used to solve the problem that the STI isolation structure in the prior art is difficult to further shrink and affect the performance of the device

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  • Manufacturing method of semiconductor device shallow-trench isolation structure
  • Manufacturing method of semiconductor device shallow-trench isolation structure
  • Manufacturing method of semiconductor device shallow-trench isolation structure

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Embodiment 1

[0045] Such as Figure 6 and Figure 8 ~ Figure 14 As shown, this embodiment provides a method for manufacturing a shallow trench isolation structure of a semiconductor device, including the following steps:

[0046] Such as Figure 6 and Figure 8 ~ Figure 10 As shown, step 1) S11 is first performed, providing a silicon substrate 201, forming a mask layer on the surface of the silicon substrate 201, and forming shallow trenches 204 in the silicon substrate 201 by photolithography.

[0047] As an example, the mask layer is a stack of silicon dioxide layer 202 and silicon nitride layer 203, and its thickness is 30 nm˜200 nm. Of course, in other embodiments, other materials such as high-k dielectric materials can also be used as the mask layer.

[0048] Specifically, in this step, a photoresist (not shown) is formed on the surface of the mask layer, and then an etching window is formed by exposure, and the silicon substrate 201 under the etching window is etched to form a sh...

Embodiment 2

[0059] Such as Figure 7 ~ Figure 15 As shown, this embodiment provides a method for manufacturing a shallow trench isolation structure of a semiconductor device, including the following steps:

[0060] Such as Figure 7 ~ Figure 10 As shown, step 1) S21 is first performed, providing a silicon substrate 201, forming a mask layer on the surface of the silicon substrate 201, and forming shallow trenches 204 in the silicon substrate 201 by photolithography.

[0061] As an example, the mask layer is a stack of silicon dioxide layer 202 and silicon nitride layer 203, and its thickness is 30 nm˜200 nm. Of course, in other embodiments, other materials such as high-k dielectric materials can also be used as the mask layer.

[0062] Specifically, in this step, a photoresist (not shown) is formed on the surface of the mask layer, and then an etching window is formed by exposure, and the silicon substrate 201 under the etching window is etched to form a shallow trench groove 204 . In...

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Abstract

The invention provides a manufacturing method of a semiconductor device shallow-trench isolation structure, which at least comprises the steps of: 1) providing a silicon substrate, forming a mask layer on the surface of the silicon substrate, and forming a shallow trench in the silicon substrate through a photoetching process; 2) forming a SiO2 isolating layer in the shallow trench, wherein the SiO2 isolating layer comprises a SiO2 filling part filled in the shallow trench, and a SiO2 projection which projects from the surface of the silicon substrate; 3) removing the mask layer, and etching the SiO2 projection to a first width; and 4) forming a semiconductor material layer with a first thickness on the silicon substrate surface at two sides of the SiO2 projection. The manufacturing method of the semiconductor device shallow-trench isolation structure has functions of: effectively reducing width of an STI, effectively enlarging the area of an active region through an epitaxial mode, enlarging a driving current of the semiconductor device, and improving integration level of the semiconductor device. The manufacturing method of the semiconductor device shallow-trench isolation structure is compatible with traditional CMOS technology and industrialization can be easily realized.

Description

technical field [0001] The invention relates to a manufacturing method of a semiconductor device, in particular to a manufacturing method of a shallow trench isolation structure of a semiconductor device. Background technique [0002] As the semiconductor process enters the deep sub-micron era, components below 0.18 microns (such as the active region of CMOS integrated circuits) are mostly fabricated using shallow trench isolation structures (STI) for lateral isolation. [0003] As a device isolation technology, the shallow trench isolation structure mainly includes: [0004] Such as Figure 1 ~ Figure 2 As shown, step 1 is firstly performed, providing a substrate 101, and sequentially forming a thermal oxide layer 102 and a silicon nitride layer 103 on its surface from bottom to top; [0005] Such as image 3 As shown, then proceed to step 2, first forming a photoresist on the surface of the silicon nitride layer 103, and forming an opening in the photoresist layer after ...

Claims

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Application Information

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IPC IPC(8): H01L21/762
CPCH01L21/76224
Inventor 赵猛
Owner SEMICON MFG INT (SHANGHAI) CORP
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