Data transmission system based on FPGA and DSP

A data transmission system and data technology, applied in the field of data processing, can solve problems such as difficulty in ensuring the continuity of FPGA and DSP data transmission, compressing DSP processing time, and increasing the difficulty of DSP real-time design, so as to reduce the difficulty of real-time design and ensure reliability The effect of transmission

Active Publication Date: 2015-01-21
四川九洲防控科技有限责任公司
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AI Technical Summary

Problems solved by technology

However, if the FPGA is only used as a wiring channel, some calculations in applications (such as modulo calculations in radar signal processing) can only be performed in the DSP, which will compress the processing time of the DSP and increase the difficulty of real-time design of the DSP. Therefore, it is difficult to guarantee the continuity of data transmission between FPGA and DSP

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  • Data transmission system based on FPGA and DSP

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Embodiment Construction

[0014] All features disclosed in this specification, or steps in all methods or processes disclosed, may be combined in any manner, except for mutually exclusive features and / or steps.

[0015] Any feature disclosed in this specification, unless specifically stated, can be replaced by other alternative features that are equivalent or have similar purposes. That is, unless expressly stated otherwise, each feature is one example only of a series of equivalent or similar features.

[0016] Such as figure 1 Shown is the functional block diagram of the data transmission system based on FPGA and DSP of the embodiment of the present invention. The data transmission system of this embodiment includes an FPGA module, a DSP module and an external memory, and the FPGA module includes a memory read-write control unit, a data processing unit, an asynchronous FIFO unit, a synchronous FIFO unit and a data read-write detection unit.

[0017] The memory read-write control unit is used to rea...

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Abstract

The invention discloses a data transmission system based on an FPGA and a DSP. The data transmission system comprises an FPGA module, a DSP module and an external memory. The FPGA module comprises a memory read-write control unit, a data processing unit, an asynchronous FIFO unit, a synchronous FIFO unit and a data read-write detection unit. The memory read-write control unit reads the data of predetermined units from the external memory. The data processing unit is used for processing the data of all the units. The asynchronous FIFO unit is used for conducting clock domain transformation on the data of the predetermined units. The synchronous FIFO unit caches the data of the predetermined units, and an interrupt signal is sent to the DSP module when data arrive at the predetermined units. The DSP module reads the data from the synchronous FIFO unit according to the interrupt signal. When the data read-write detection unit detects that the DSP module reads the data of one unit every time, a feedback signal is sent to the memory read-write control unit, so that the memory read-write control unit reads the data of the next unit from the external memory. The data transmission system based on the FPGA and the DSP can guarantee the data transmission continuity between the FPGA and the DSP under an EMIF transmission mode.

Description

technical field [0001] The invention relates to the technical field of data processing, in particular to a data transmission system based on FPGA and DSP. Background technique [0002] FPGA (Field Programmable Gate Array, Field Programmable Gate Array) + DSP (digital signal processing, digital signal processing) architecture is the most commonly used digital signal processing solution. FPGA is used to complete high-speed processing of big data, and DSP is used to complete post-complex processing. In most applications, FPGA is used to realize high-speed real-time processing of large amounts of data. However, the internal storage space of FPGA is relatively small, so external memory is generally used to store data. FPGA reads data from external memory and sends an interrupt signal to DSP after processing. , the DSP actively reads data from the FPGA for the next step of processing after receiving the interrupt signal. [0003] However, in the face of large data transmission, ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F13/38
CPCG06F13/24G06F13/4068
Inventor 罗大鑫许刚
Owner 四川九洲防控科技有限责任公司
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