Check patentability & draft patents in minutes with Patsnap Eureka AI!

Preparation method of fin layer photo-etching alignment mark

A lithography alignment and marking technology, applied in electrical components, electrical solid state devices, circuits, etc., can solve the problems of increasing lithography processes, increasing process steps and manufacturing costs, etc.

Active Publication Date: 2015-03-11
SHANGHAI INTEGRATED CIRCUIT RES & DEV CENT
View PDF4 Cites 12 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, adding an additional photolithography process obviously increases the process steps and manufacturing cost

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Preparation method of fin layer photo-etching alignment mark
  • Preparation method of fin layer photo-etching alignment mark
  • Preparation method of fin layer photo-etching alignment mark

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0035] In order to make the content of the present invention clearer and easier to understand, the content of the present invention will be further described below in conjunction with the accompanying drawings. Of course, the present invention is not limited to this specific embodiment, and general replacements known to those skilled in the art are also covered within the protection scope of the present invention.

[0036] The preparation method of the fin layer photolithographic alignment mark used in the fin transistor process of the present invention improves the self-alignment double patterning process of the side wall hard mask, and aligns the conventional area with the photolithography when designing the layout The layout of the sacrificial layer at the mark is designed separately, the layout of the sacrificial layer in the conventional area remains unchanged, and the spacing and width of the sacrificial layer pattern in the sacrificial layer layout at the photolithograph...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The invention provides a preparation method of a fin layer photo-etching alignment mark. By designing the width and the spacing of a sacrificial layer pattern on the photo-etching alignment mark in a designed layout, according to a self-alignment double patterning process of a side wall hard mask, etching the sacrificial layer, depositing and etching a side wall medium layer, etching a fin, and filling up the spacing of the sacrificial layer pattern on the photo-etching alignment mark by the deposited side wall medium layer, and enabling the fin width on the photo-etching alignment mark to be equal to the spacing of the sacrificial layer pattern and greater than the fin standard width. And therefore, on the condition of not increasing an extra photo-etching process, the fin width on the photo-etching alignment mark is effectively increased, and the proportion of the tin area to the total area of the photo-etching alignment mark area is increased, so that the optical recognition rate and the optical alignment precision of the photo-etching alignment mark are remarkably improved.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a method for preparing a fin layer photolithographic alignment mark used in fin transistor technology. Background technique [0002] With the advancement of integrated circuit manufacturing technology, the traditional planar bulk silicon CMOS has been unable to overcome the shortcomings of large leakage current and small conduction current. It must adopt a three-dimensional fin transistor (FinFET) device structure, and Intel took the lead in realizing it at the 22nm node. Produce. [0003] Compared with planar CMOS, the most important change of the three-dimensional fin transistor is to change the active region from a planar block shape to a discrete three-dimensional fin (Fin) shape, and each fin has the same width. Due to the small fin width (15nm in Intel's 22nm process) and tight pitch (60nm in Intel's 22nm process), it exceeds the resolution limit of the most advance...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
IPC IPC(8): H01L23/544
Inventor 李铭袁伟
Owner SHANGHAI INTEGRATED CIRCUIT RES & DEV CENT
Features
  • R&D
  • Intellectual Property
  • Life Sciences
  • Materials
  • Tech Scout
Why Patsnap Eureka
  • Unparalleled Data Quality
  • Higher Quality Content
  • 60% Fewer Hallucinations
Social media
Patsnap Eureka Blog
Learn More

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic, Popular Technical Reports.

© 2025 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap|About US| Contact US: help@patsnap.com