Wafer level package structure and technological method thereof

Abstract

The invention relates to a wafer level package structure and a technological method thereof. The wafer level package structure comprises a lead frame (1). A chip (2) is arranged on the lead frame (1) in an inversion mode. A metal bump (3) is arranged on the front face of the chip (2). The metal bump (3) is connected with the chip (2) through a solder ball (4). Non-conducting glue (5) is arranged on the periphery of the metal bump (3) and the periphery of the solder ball (4). A molding compound (6) is packaged on the periphery of the lead frame (1). A metal layer (7) is electroplated on the back face of the lead frame (1). According to the wafer level package structure and the technological method of the wafer level package structure, the drawing design on a wafer completely corresponds to a drawing of the lead frame, the whole chip is installed on the lead frame in the inversion mode and then is cut, separated and packaged, and wafer level package that the single chip size is equal to a single unit of the lead frame is achieved.

Description

technical field [0001] The invention relates to a wafer-level packaging structure and a process method thereof, belonging to the technical field of semiconductor packaging. Background technique [0002] In the existing wafer-level packaging, the wafer is firstly diced, and the front side of the separated chip after scribing is pasted on the carrier board, and then the side of the carrier board where the chip is pasted is plastic-sealed, and the carrier board is removed to expose the front side of the chip. , Perform Fanout rewiring on the front electrode of the chip to make the metal circuit and the electrical output of the product. After the wafer is diced, the individual chips are arranged and pasted on the carrier board for encapsulation and fanout metal circuit production. On the one hand, the alignment efficiency of the chips is low, and the alignment of the separated chips is prone to displacement deviation, which will cause subsequent chip fronts Offset of the fanout...

AI Technical Summary

Problems solved by technology

After the wafer is diced, the individual chips are arranged and pasted on the carrier board for encapsulation and fanout metal circuit production. On the one hand, the alignment efficiency of the chips is low, and the alignment of the separated chips is prone to displacement deviation, which will cause subsequent chip fronts The offset of the fanout metal circuit; because the fanout packaging of the wafer is carried out in the packaging factory, it is relatively difficult for the packaging factory to manufacture the fine-pitch circuits involved in the fanout process, and it is prone to problems of circuit short circuit and circuit stripping, and the yield rate is low

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