Three-dimensional on-chip optical network topology and routing path calculation method

Abstract

The present invention provides a three-dimensional on-chip optical network topology and a routing path calculation method. The three-dimensional on-chip optical network topology includes: N optical routing layers, each of which includes N rows×N columns of optical routers, each The optical router is connected to an IP core, and each optical router of at least one optical routing layer is connected to a vertical optical router, wherein, the N is a natural number greater than or equal to 3. Each of the optical routers is connected to adjacent optical routers, and the first optical router in each row or column is also connected to the last optical router in the row or column, and each of the vertical optical routers is connected to another optical router. The optical routers at corresponding positions in the two optical routing layers are connected, thereby reducing chip resource consumption and reducing the maximum chip area.

Description

[0001] Technical field: [0002] The invention relates to communication technology, in particular to a three-dimensional on-chip optical network topology and a routing path calculation method. [0003] Background technique: [0004] In the mid-1990s, integrated circuits began to transform into integrated systems, and SoCs came into being. System-on-chip integrates various types of integrated circuits into a single chip, making system-level products portable. However, with the rapid development of CMOS technology, it is urgent to design a new architecture to relieve the communication pressure of the system on chip by decoupling various types of integrated circuits from the shared bus channel. The network on chip is to implant computer network technology into the chip design, which fundamentally solves the above-mentioned communication problem of the system on chip based on the shared bus. However, as the number of IP cores in a single chip continues to increase, the high energ...

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Problems solved by technology

[0006] The existing three-dimensional on-chip optical network uses a network topology structure, which has the problem of large zero-load transmission delay. In addition, the current three-dimensional on-chip network mostly uses homogeneous optical routers, and the deployment of components inside each optical router is relatively redundant. As a result, chip resources such as optical crossbar switches are seriously wasted

[0007] For the routing algorithm of 3D on-chip network, dimension order routing is widely used. However, this routing algorithm can only calculate a macroscopic optical path for each packet message, and the microscopic packet message forwarding path inside each node through which the optical path passes cannot be determined. computational

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