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Trigger unit single event upset effect experimental verification circuit

A single event flipping and verifying circuit technology, which is applied in the field of trigger unit single event flipping effect experimental verification circuit, can solve the problem of large power consumption without considering the flip-flop data, without considering the jump of the input signal, and increasing the complexity of the evaluation method and other problems, to achieve the effect of avoiding large transient power consumption, reducing instantaneous voltage drop, and high reliability

Active Publication Date: 2015-04-08
NO 771 INST OF NO 9 RES INST CHINA AEROSPACE SCI & TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Existing evaluation methods directly rely on the radiation-hardened integrated circuit itself, and connect the flip-flop units inside the circuit end-to-end using design-for-test techniques to evaluate the anti-single event upset capability of the flip-flop; but this method not only increases The complexity of the evaluation method, and the accuracy of the experimental results may be affected by the bombardment of other units inside the circuit by single particles
In the prior art, the single-event-reversal evaluation circuit of the independent flip-flop unit simply uses a flip-flop chain and fixes the input level of "0" or "1" at the output end of the flip-flop chain, without taking into account the occurrence of the input signal. The jumping situation does not consider the large power consumption problem caused when the trigger data is large

Method used

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  • Trigger unit single event upset effect experimental verification circuit
  • Trigger unit single event upset effect experimental verification circuit
  • Trigger unit single event upset effect experimental verification circuit

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Embodiment Construction

[0022] The present invention will be further described in detail below in conjunction with specific embodiments, which are explanations of the present invention rather than limitations.

[0023] The present invention is a flip-flop unit single event flip effect experimental verification circuit, such as figure 2 As shown, it includes a high / low level generation circuit 811, a shift register chain A812 and a shift register chain B814, and a daisy-chained clock tree network 813 and a high level detection circuit 816; a high / low level generation circuit 811 The input terminal of the high / low level generating circuit 811 is connected with the clock signal clk, and the output terminal of the high / low level generating circuit 811 outputs the periodic high and low level signal data, and is connected with the input terminals of the shift register chain A and the shift register chain B; The input end of the bit register chain A812 is also connected to the output ends clka1˜clkan of th...

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PUM

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Abstract

The invention discloses a trigger unit single event upset effect experimental verification circuit. The trigger unit single event upset effect experimental verification circuit comprises a high / low level generating circuit, a shift register chain A, a shift register chain B, a comparison circuit and a high level detection circuit, wherein a clock signal is input through the input end of the high / low level generating circuit; the shift register chain A and the shift register chain B are equal in shift register cascade stages; the comparison circuit and the high level detection circuit are connected in sequence; the high / low level generating circuit is used for generating periodic high and low level signals which are simultaneously input into the shift register chain A and the shift register chain B according to a clock signal; the clock input end of each register in the shift register chain A and the shift register chain B is connected with the clock signal respectively; the data output end of the shift register chain A and the data output end of the shift register chain B are connected to the two input ends of the comparison circuit respectively; when the states of data input into the two input ends of the comparison circuit at the same moment are consistent, the output end of the comparison circuit outputs a low level; when the states of data input into the two input ends of the comparison circuit at the same moment are inconsistent, the output end of the comparison circuit outputs a high level; the high level detection circuit is used for identifying the output signal of the comparison circuit and counting the high level.

Description

technical field [0001] The invention relates to the field of semiconductor integrated circuits, in particular to an experimental verification circuit and method for the single event flipping effect of a trigger unit. Background technique [0002] The space environment contains a variety of particles, such as electrons, photons, protons, alpha particles, and heavy particles, all of which will interfere with microelectronic devices or integrated circuits and have a negative impact, resulting in failure of spacecraft, the so-called space radiation effect. One of the most serious and common effects of space radiation is the single event effect, which can directly change the state of the data stored in the flip-flop unit, thus making the integrated circuit work abnormally. Therefore, the field of aerospace applications puts forward high reliability and radiation resistance requirements for semiconductor integrated circuits. [0003] At present, the design of radiation-resistant...

Claims

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Application Information

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IPC IPC(8): G01R31/00G01R31/28
Inventor 李海松蒋轶虎杨博赵德益王鹏卢红利李彤唐威吴龙胜
Owner NO 771 INST OF NO 9 RES INST CHINA AEROSPACE SCI & TECH
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