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High-speed QC-LDPC encoder based on three-stage assembly line

A pipeline and encoder technology, applied in the field of channel encoding, can solve the problems of slow encoding speed, high circuit cost, large memory, etc., and achieve the effect of improving throughput, simple structure, and improving encoding speed

Inactive Publication Date: 2015-04-15
RONGCHENG DINGTONG ELECTRONICS INFORMATION SCI & TECH CO LTD
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

This scheme has two disadvantages: one is that a large amount of memory is required, resulting in high circuit cost; the other is that the information bits are serially input, and the encoding speed is slow

Method used

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  • High-speed QC-LDPC encoder based on three-stage assembly line
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  • High-speed QC-LDPC encoder based on three-stage assembly line

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Embodiment Construction

[0017] The preferred embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings, so that the advantages and features of the present invention can be more easily understood by those skilled in the art, so as to define the protection scope of the present invention more clearly.

[0018] The row and column weights of a circular matrix are the same, denoted as w. If w=0, then the circulant matrix is ​​an all-zero matrix. If w=1, then the circulant matrix is ​​permutable, called a permutation matrix, which can be obtained by cyclically shifting the identity matrix I to the right by several bits. The check matrix H of the QC-LDPC code is composed of c×t b×b order circulant matrices H j,k (1≤j≤c, 1≤k≤t, t=e+c) constitute the following array:

[0019]

[0020] Usually, any circulant matrix in the parity check matrix H is either an all-zero matrix (w=0) or a permutation matrix (w=1). Let the circular matrix H j,k the firs...

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Abstract

The invention provides a high-speed QC-LDPC (quasi-cyclic low-density parity-check) encoder based on a three-stage assembly line. The encoder comprises a sparse matrix and vector multiplier, a type-I backward iterative circuit and a type-II backward iterative circuit, wherein the sparse matrix and vector multiplier is used for sparse matrix and vector multiply operation; the type-I backward iterative circuit and the type-II backward iterative circuit are used for backward iterative operation; the whole encoding process is divided into three assembly line stages. The high-speed QC-LDPC encoder provided by the invention has the advantages of simple structure, low cost, high throughput capacity and the like.

Description

technical field [0001] The invention relates to the field of channel coding, in particular to a high-speed QC-LDPC encoder based on a three-stage pipeline in a communication system. Background technique [0002] Low-Density Parity-Check (Low-Density Parity-Check, LDPC) code is one of efficient channel coding techniques, and Quasi-Cyclic LDPC (QC-LDPC) code is a special LDPC code. Both the generation matrix G and the check matrix H of the QC-LDPC code are arrays composed of circulant matrices, which have the characteristics of a segmented cycle, so they are called QC-LDPC codes. The first row of the circulant matrix is ​​the result of the cyclic right shift of the last row by 1 bit, and the remaining rows are the result of the cyclic right shift of the previous row by 1 bit. Therefore, the circulant matrix is ​​completely characterized by its first row. Usually, the first row of a circulant matrix is ​​called its generator polynomial. [0003] The communication system usual...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03M13/11
Inventor 张鹏刘志文张燕
Owner RONGCHENG DINGTONG ELECTRONICS INFORMATION SCI & TECH CO LTD
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