Manufacturing method for interconnected through holes in wafer level chip size packaging

Abstract

The invention discloses a manufacturing method for interconnected through holes in wafer level chip size packaging. The method comprises the steps of removing stopping materials on a welding pad by the etching method; paving photoresist in the whole opening and on the rear surface of a substrate so as to form a photoresist layer; exposing and developing to remove the photoresist layer above the welding pad; removing a dielectric layer above the welding pad by the dry etching method. The method is simple and easy to be carried out; in addition, the dielectric layer on the welding pad is removed by dry etching, and thus problem that the upper dielectric layer on the welding pad is not etched but is completely removed, and an insulating layer on the rear surface of a wafer is etched to be thin or completely used to lead to short circuit of a line can be avoided. With the adoption of the method, the process of forming silicon through hole interconnection by the etching method can be simplified; the wafer level chip size packaging is simplified; therefore, the packaging efficiency is increased, and meanwhile, the packaging reliability is improved.

Description

technical field [0001] The invention relates to wafer-level chip size packaging, in particular to a method for making through-hole interconnections in wafer-level chip size packaging. Background technique [0002] The popularization of portable consumer electronic products and consumers' demand for such products has made the function and high integration of IC chips more and more demanding. In order to meet this requirement, the package size is required to be light, thin and short, and the transmission speed is increased. Therefore, it is often necessary to form a vertical through-silicon via interconnection structure. [0003] The existing packaging method adopts wafer-level chip size packaging, and the general structure of the wafer is as follows: figure 1 As shown, the wafer includes several chip units, and each chip unit includes a base 1 and a dielectric layer 3 located on the front side of the base. The front side of the base is provided with an element area 4, and se...

AI Technical Summary

Problems solved by technology

In the above etching method, after the opening is formed, the dielectric layer on the pad must be removed by etching first, and then the insulating layer is laid. The thickness of the two layers of material is greater than the thickness of the insulating layer on the back of the wafer. There will be a phenomenon that the insulating layer on the plane is etched away before the pad is exposed. If the insulating layer on the plane is too thin or there is no insulating layer, the subsequent packaging process will cause a short circuit in the

Affects the reliability of packaged chips, and the process steps are more complicated

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