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Semiconductor wafer level package structure

A wafer-level packaging and semiconductor technology, which is applied to semiconductor devices, semiconductor/solid-state device parts, electric solid-state devices, etc., can solve problems such as cracks and device failures, and improve mechanical strength, disperse external forces, and improve reliability performance Effect

Inactive Publication Date: 2015-05-13
NANTONG FUJITSU MICROELECTRONICS
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] Although this semiconductor device chip-level packaging structure adopts a structure of two dielectric layers, which increases the mechanical reliability of the entire packaging structure to a certain extent, the metal gap formed between the copper layer electrodes 6 and the metal solder balls 7 Compounds are prone to cracks due to stress, resulting in device failure

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  • Semiconductor wafer level package structure
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Embodiment Construction

[0020] Embodiments of the present invention will be described below with reference to the drawings. Elements and features described in one drawing or one embodiment of the present invention may be combined with elements and features shown in one or more other drawings or embodiments. It should be noted that representation and description of components and processes that are not related to the present invention and known to those of ordinary skill in the art are omitted from the drawings and descriptions for the purpose of clarity.

[0021] see figure 2 Shown is a structural diagram of the semiconductor wafer level packaging structure of the present invention.

[0022] In this embodiment, the semiconductor wafer level packaging structure includes a semiconductor chip 101 , a redistribution electrode 201 , a redistribution electrode layer 401 and metal solder balls 501 .

[0023] The rewiring electrodes 201 are formed on the semiconductor chip 101 . For example, the redistri...

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Abstract

The invention relates to a semiconductor wafer level package structure. The semiconductor wafer level package structure comprises a semiconductor chip, a rewiring electrode, a reformed electrode layer, a metal tin ball and a resin layer, wherein the rewiring electrode is formed on the semiconductor chip; the reformed electrode layer is formed on the rewiring electrode; the metal tin ball is welded with the reformed electrode layer; the resin layer covers the metal tin ball, and the thickness of the resin layer is smaller than the height of the metal tin ball. The semiconductor wafer level package structure is high in mechanical reliability; the probability of failure of the whole package structure can be reduced in case of uneven stress.

Description

technical field [0001] The invention relates to a semiconductor packaging technology, in particular to a semiconductor wafer level packaging structure. Background technique [0002] In order to achieve high mechanical reliability of wafer-level packaging in large-size chips, more products have begun to use a structure with two layers of metal and two layers of dielectric layers to connect metal solder ball terminals and chip surface electrodes. [0003] see figure 1 Shown is the existing semiconductor device wafer level packaging structure. There are electrodes 2 on the semiconductor chip 1, the dielectric layers 3 and 4 are formed by coating photolithography, and then the rewiring 5 and copper layer electrodes 6 are formed by electrolytic chemical plating, and finally connected with the metal solder ball 7 by welding ,form figure 1 The semiconductor device wafer-level packaging structure shown. [0004] Although this semiconductor device chip-scale packaging structure a...

Claims

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Application Information

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IPC IPC(8): H01L23/488H01L23/485H01L23/31
CPCH01L2224/11
Inventor 徐小锋
Owner NANTONG FUJITSU MICROELECTRONICS