Flash storage unit and preparation method thereof
A flash memory storage and hard mask technology, applied in electrical components, semiconductor/solid-state device manufacturing, transistors, etc., which can solve problems such as increased contact area gate coupling coefficient, low flash memory erasing speed, and low memory cell rated leakage current. , to achieve the effect of improving gate coupling coefficient, increasing contact area, increasing rated leakage current and erasing speed
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Embodiment 1
[0058] Such as Figure 5 to Figure 18 Shown, the present invention provides a kind of preparation method of flash storage unit, and described preparation method comprises the following steps at least:
[0059] First perform step 1), such as Figure 5 Middle S201 and Figure 6 As shown, a semiconductor substrate 400 is provided with a tunnel oxide material layer 401, a floating gate material layer 402, a first hard mask 403, a second hard mask 404, and a photoresist 405 sequentially formed from bottom to top. The photoresist 405 is patterned, and part of the photoresist 405 is removed until the second hard mask 404 is exposed, so as to form the photoresist 405 including at least one strip structure. Wherein, the material of the first hard mask 403 includes at least silicon nitride; the material of the second hard mask 404 includes at least silicon nitride or silicon oxide; the material of the semiconductor substrate 400 includes at least silicon, silicon germanium, silicon o...
Embodiment 2
[0077] like Figure 18 As shown, the present invention also provides a flash storage unit, which at least includes: an active region 4001, a tunnel oxide layer 401, a floating gate 402 with an even number of raised structures 4021, a blocking oxide layer 409, a control gate 410 and an isolation structure 407.
[0078] The active region 4001 is isolated from the semiconductor substrate 400 by an isolation structure 407; a tunnel oxide layer 401, a floating gate 402 with an even number of raised structures 4021, and a blocking oxide layer are sequentially formed on the active region 4001. layer 409 and control gate 410 .
[0079] The material of the semiconductor substrate 400 includes at least silicon, silicon germanium, silicon on insulating layer (silicon on insulator, SOI), silicon germanium on insulating layer (silicon germanium on insulator, SGOI) or germanium on insulating layer (germanium on insulator, GOI) , in this embodiment, the material of the semiconductor substr...
Embodiment 3
[0082] The preparation method of each step of the third embodiment is basically the same as that of the first embodiment, except that the number of stripe structures of the photoresist 405 in step 1) and the first hard mask caused by the change of the number The number of strip structures of the film 403 and the number of sidewall structures 406 are related to the corresponding changes of the number of raised structures 4021 of the floating gate 402 , and the rest of the similarities will not be repeated here.
[0083] like Figure 19 As shown, in one memory cell of this embodiment, preferably, the number of striped structures of the photoresist 405 in step 1) is two, and at the same time, the width of the striped structures of the photoresist 405 is the same as The spacing of the strip-like structures is equal, and the width of each of the strip-like structures is equal, but it is not limited thereto. In another embodiment, the number of the strip-like structures can be more ...
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