Method for realizing server hardware acceleration by using FPGA (field programmable gate array)

A hardware acceleration and server technology, applied in the computer field, can solve problems such as low efficiency, large memory access delay, and consistency impact, and achieve the effects of strong practicability, high bus bandwidth, and improved computing speed

Inactive Publication Date: 2015-05-27
LANGCHAO ELECTRONIC INFORMATION IND CO LTD
View PDF5 Cites 28 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

For the data that needs to be frequently exchanged between the CPU and the accelerator, due to

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Method for realizing server hardware acceleration by using FPGA (field programmable gate array)

Examples

Experimental program
Comparison scheme
Effect test

Example Embodiment

[0030] Example:

[0031] Taking the realization of the image processing accelerator as an example, firstly, the hardware description language (HDL) is used to realize the image processing algorithm acceleration module in the FPGA. Since image data generally requires a large storage space, a storage controller can be instantiated in the FPGA, and a storage chip outside the FPGA is connected as the private memory space of the FPGA. Then implement the QPI bus module, in which the protocol table of the protocol layer can be simplified according to the system structure. Then implement the Cache module and the message forwarding module in the FPGA. An address decoding table is set in the message forwarding module to correctly map the addresses that the FPGA image processing module needs to access to the FPGA private memory space and the system memory space. The hardware accelerator system described in HDL language is synthesized and placed and routed, and the executable bit stream...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

PUM

No PUM Login to view more

Abstract

The invention discloses a method for realizing server hardware acceleration by using an FPGA (field programmable gate array). A specific realizing process of the method comprises the following steps: constructing a QPI (quick path interconnect) bus module, a hardware acceleration module, a high-speed buffer storage region and a message conversion module in the FPGA, wherein the massage conversion module is used for converting memory reading-writing operation launched by the hardware acceleration module into a series of QPI messages and sending the QPI messages to the QPI bus module, and sending reading-writing response returned by the QPI bus to the hardware acceleration module. Compared with the prior art, the method for realizing server hardware acceleration by using the FPGA disclosed by the invention can configure different acceleration algorithms for different computational scenes by virtue of the reconfigurability of the FPGA, is relatively high in flexibility and expansibility. The QPI bus is utilized to access a memory space of the system, so that higher bandwidth and smaller memory accessing delay, in comparison with those of a mainstream PCIe bus, are provided.

Description

technical field [0001] The invention relates to the technical field of computers, in particular to a highly practical server hardware acceleration method realized by FPGA. Background technique [0002] With the continuous expansion of computer application fields, various application scenarios also put forward higher and higher requirements for the data processing capabilities of servers. It is often difficult for servers to achieve balanced allocation of resources when they are used in scenarios that emphasize certain functions. To achieve the required processing speed, more powerful computing power is required, but this often means a large cost input. On the other hand, in some occasions that have strict requirements on data processing speed, it is difficult for ordinary servers to perform these tasks. At present, the more common solution is to share a part of the work of the central processing unit (CPU) by the hardware accelerator to undertake certain types of specific ...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

Application Information

Patent Timeline
no application Login to view more
IPC IPC(8): G06F13/38G06F13/42
Inventor 岳自超童元满李仁刚
Owner LANGCHAO ELECTRONIC INFORMATION IND CO LTD
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Try Eureka
PatSnap group products

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic.

© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap