Through hole etching method
A technology of through-hole etching and etching layer, which is applied in the field of flat panel display device manufacturing, can solve the problems of over-etching of the etch stop layer, and achieve the effects of avoiding film layer damage, avoiding damage, and improving yield
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Embodiment 1
[0036] This embodiment provides a method for etching through holes, including the following steps:
[0037] S1, such as Figure 2a As shown, a photoresist layer 14 is coated on the surface of the substrate 100 to be etched, and a through-hole pattern is formed by a photolithography process. The substrate 100 is sequentially divided into a first etching layer 11, a second etching layer 11, and a first etching layer 11 along the thickness direction according to the depth of the through-hole. Two etching layers 12 and an etching stop layer 13 , the first etching layer 11 is disposed close to the photoresist layer 14 , and the thicknesses of the first etching layer 11 and the second etching layer 12 are equal to the depth of the through hole 7 .
[0038] The diameter of the through hole required in this embodiment is 3 μm, and the depth is 350 nm; the through hole etching method described in the present invention can etch through holes of any size, but in order to reflect the thro...
Embodiment 2
[0051] This embodiment provides a method for through hole etching, and the specific steps are the same as in Embodiment 1, such as Figure 5 As shown, the only difference is that the substrate 100 in this embodiment is a thin film transistor, and the thin film transistor includes a substrate 1, a buffer layer 2 directly disposed on the substrate 1, and semiconductor layers disposed on the buffer layer 2 in sequence. 3. The gate insulating layer 4, the gate layer 5 and the interlayer insulating layer 6. The via hole 7 to be prepared is provided through the gate insulating layer 4 and the interlayer insulating layer 6, and the connection source / The drain and the channel of the semiconductor layer 3.
[0052] In this embodiment, the buffer layer 2 is a silicon dioxide layer with a thickness of The semiconductor layer 3 is a polysilicon layer, The gate insulating layer 4 is an amorphous silicon dioxide layer, The gate 5 molybdenum-tungsten layer, The interlayer insulating...
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